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Bin L Liu

from Sunnyvale, CA
Age ~40
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Related to:
Liao Yun, 51Yingxue Li, 44Rui Liu, 43Yan Cao Liu, 36Wenshuo Liu, 40Song Liu, 46Haiyan Liu, 37Zhengye Liu, 47Pu Liu Yi, 40Qiao Bin Liu, 51Yali Liu, 45Sally X Liu, 48Mingqing Xiao, 60Kuang Liu
Connected to:
Adela Liu, 73Alec X Liu, 39Alpha T Liu, 46Amon Y Liu, 58Andrea Y Liu, 46Anqi Liu, 39Arden K Liu, 64Ba S Liu, 62Bailu Liu, 35Ban Liu, 48

Bin Liu Phones & Addresses

  • 830 Lois Ave, Sunnyvale, CA 94087
  • San Jose, CA
  • Pleasanton, CA
  • Lafayette, CA
  • Davis, CA

Resumes

Resumes

Bin Liu Photo 1

Bin Liu San Jose, CA

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Work:
CISCO SYSTEMS

Jul 2010 to 2000
Program Manager, Supply Chain Network Design & Management
CISCO SYSTEMS
San Jose, CA
Jun 2008 to Jul 2010
Program Manager, Supply Chain Planning and Operation
CISCO SYSTEMS
San Jose, CA
Jul 2007 to May 2008
Project Manager, WW Reverse Logistics & Distribution Channel Return Operations
TELUS MOBILITY
Toronto, ON
May 2003 to Jan 2007
Senior Business Analyst, Engineering Group
Beissbarth GmbH

May 1994 to Jun 1999
National Operations Manager
Education:
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Cambridge, MA
2007
M.E., Supply Chain Management in Supply Chain design and Strategy
George Mason University
Fairfax, VA
2001
M.S. in Operations Research and Management Science
BEIJING INSTITUTE OF TECHNOLOGY
1992
BEng in Mechanical Engineering
Skills:
Program Management, Demand & Planning, Inventory management, Predictive Data Analytics, Data visualization, Supply Chain Resiliency, Supply chain taxes and duty, Chinese
Bin Liu Photo 2

Bin Liu Union City, CA

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Work:
ChemTrace

Jan 2013 to 2000
Research Scientist
Quantum Global Technologies, LLC
Fremont, CA
May 2011 to Dec 2012
Lab Reporting Analyst II
Applied Materials
Fremont, CA
Dec 2005 to May 2011
Lab Reporting Analyst I
Education:
University of California at Berkeley
Berkeley, CA
2001 to 2005
Bachelor in Applied Mathematics
UC Berkeley

Business Records

Name / Title
Company / Classification
Phones & Addresses
Bin Liu
President
MOLECULAR IMAGING & THERAPEUTICS INCORPORATED
185 Berry St, San Francisco, CA 94107
650 Page Ml Rd, Palo Alto, CA 94304
2522 1700 4 St, San Francisco, CA 94158
Bin Liu
Principal
Bin Liu Tax Service
Services-Misc
2850 Sierra Rd, San Jose, CA 95132
Bin Liu
Cheering International Education LLC
4516 Macbeth Ave, Fremont, CA 94555
Bin Liu
President
Mobert Semiconductor USA, Inc
Mfg Semiconductors/Related Devices
111 Msn Rdg Ct, Fremont, CA 94539
Bin Liu
President
THREE-RING GROUP, INC
2722 Prince St, Berkeley, CA 94705

Publications

Us Patents

High Noise Rejection Voltage-Controlled Ring Oscillator Architecture

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US Patent:
6414557, Jul 2, 2002
Filed:
Feb 17, 2000
Appl. No.:
09/507114
Inventors:
Bin Liu - Danville CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03B 502
US Classification:
331 57, 327261, 327266, 327272, 327274
Abstract:
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).

Image-Rejection I/Q Demodulators

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US Patent:
6560449, May 6, 2003
Filed:
Jun 12, 2000
Appl. No.:
09/591925
Inventors:
Bin Liu - Danville CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 110
US Classification:
455302, 455205
Abstract:
In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver includes an I demodulator and a Q demodulator. A local oscillator (LO) signal is provided by a PLL to a quadrature LO generator that provides an LO_I signal to an I demodulator and an LO_Q signal to a Q demodulator. The LO_I and LO_Q signals are amplitude and phase-controlled versions of the LO signal. An image/signal ratio (I/S) detector detects the relative phase difference and the relative amplitude difference between the respective output terminals of the I demodulator and the Q demodulator and applies an amplitude control signal and a phase control signal to corresponding amplitude control and phase control inputs of the quadrature LO generator. The I/S detector calibrates the quadrature LO generator during the interstitial interval between the reception of data packets. The control signals from the I/S detector adjust the relative amplitude and phase of the LO_I and LO_Q signals in a manner that reduces the image response of the communications receiver.

High Noise Rejection Voltage-Controlled Ring Oscillator Architecture

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US Patent:
6657503, Dec 2, 2003
Filed:
Apr 25, 2002
Appl. No.:
10/131963
Inventors:
Bin Liu - Danville CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03B 2700
US Classification:
331 57, 331183, 331185, 327261, 327266, 327272, 327274
Abstract:
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).

Receiver Architecture Employing Low Intermediate Frequency And Complex Filtering

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US Patent:
6778594, Aug 17, 2004
Filed:
Jun 12, 2000
Appl. No.:
09/592016
Inventors:
Bin Liu - Danville CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 138
US Classification:
375222, 455302
Abstract:
A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input amplifier coupled to a carrier signal. Respective I and Q demodulators are coupled to the output of the input amplifier. A quadrature local oscillator (LO) generator provides respective LO_I and LO_Q inputs to the I demodulator and LO_Q inputs to the I demodulator and to the Q demodulator. The quadrature LO generator is driven by a phase-locked LO, and the LO frequency is such that an IF of, in one embodiment, approximately 1 MHz results. The I demodulator and Q demodulator outputs are applied through respective A/D converters to a polyphase filter. The polyphase filter outputs are then processed by a digital I/Q demodulator. Although a low IF is not generally understood to promote the image rejection performance of a receiver, substantial image rejection is afforded by the polyphase filter, thereby enabling the receiver to be realized almost entirely as a monolithic integrated semiconductor device.

High Noise Rejection Voltage-Controlled Ring Oscillator Architecture

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US Patent:
6828866, Dec 7, 2004
Filed:
Oct 6, 2003
Appl. No.:
10/679839
Inventors:
Bin Liu - Danville CA
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03B 532
US Classification:
331 57, 331185, 331183, 327274
Abstract:
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. âEach differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).

High Noise Rejection Voltage-Controlled Ring Oscillator Architecture

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US Patent:
6963251, Nov 8, 2005
Filed:
Nov 18, 2004
Appl. No.:
10/992426
Inventors:
Bin Liu - Danville CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03B005/02
US Classification:
331 57, 327261, 327266, 327272, 327274
Abstract:
A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e. g. , a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e. g. , a ground terminal).

Enhanced Interleave Type Error Correction Method And Apparatus

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US Patent:
6981197, Dec 27, 2005
Filed:
Jan 23, 2002
Appl. No.:
10/057831
Inventors:
Bin Liu - Newark CA, US
Edmun ChianSong Seng - Singapore, SG
UttHeng Kan - Singapore, SG
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G11C029/00
US Classification:
714765
Abstract:
An enhanced interleave type error correction method is provided in which decoding of an enhanced interleave block is done. Subsequently the decoding may be done by decoding the estimated codewords multiple times using a single error correction code. In addition, a decoder and a digital communication system for implementing the enhanced interleave type error correction method are provided.

Image-Rejection I/Q Demodulators

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US Patent:
7184737, Feb 27, 2007
Filed:
Mar 21, 2003
Appl. No.:
10/394981
Inventors:
Bin Liu - Danville CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 1/10
H04B 17/00
US Classification:
455302, 455 6713, 4551154, 330109, 375219
Abstract:
In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver includes an I demodulator and a Q demodulator. A local oscillator (LO) signal is provided by a PLL to a quadrature LO generator that provides an LO_I signal to an I demodulator and an LO_Q signal to a Q demodulator. The LO_I and LO_Q signals are amplitude and phase-controlled versions of the LO signal. An image/signal ratio (I/S) detector detects the relative phase difference and the relative amplitude difference between the respective output terminals of the I demodulator and the Q demodulator and applies an amplitude control signal and a phase control signal to corresponding amplitude control and phase control inputs of the quadrature LO generator. The I/S detector calibrates the quadrature LO generator during the interstitial interval between the reception of data packets. The control signals from the I/S detector adjust the relative amplitude and phase of the LO_I and LO_Q signals in a manner that reduces the image response of the communications receiver.

Isbn (Books And Publications)

High Performance Switches And Routers

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Author

bin Liu

ISBN #

0470053674

Zen Yang Yong Fa Lu Bao Hu Zi Ji: Zui Xin Sheng Huo Shi Yong Fa Lu Shou Ce

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Author

bin Liu

ISBN #

7507702006

Guan Yu Ji Chu Jiao Yu Di Si Kao

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Author

bin Liu

ISBN #

7532028143

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Bin L Liu from Sunnyvale, CA, age ~40 Get Report