Jonathan Ho

6569576, May 27, 2003

Sep 27, 2000

09/672167

Shih-Cheng Hsueh - Fremont CA
Kevin T. Look - Fremont CA
Jonathan Jung-Ching Ho - Fremont CA

Xilinx, Inc. - San Jose CA

G03F 900

430 5, 430396

A reticle and pellicle that are modified to prevent ESD damage to the masking material between portions of the lithographic mask pattern on the reticle during an integrated circuit fabrication process. The modification involves providing conducting lines on the glass side of the reticle and on the surface of the pellicle to balance any buildup of electrostatic charges on those devices, thereby reducing or eliminating the induction of opposite charges onto adjacent mask pattern features on the reticle and preventing the melting and bridging of those mask pattern features and the defects caused by such melting or bridging. The conductive metal lines may have a smaller width than the smallest resolution value of the reduction lens used in the mask pattern transfer process, and may also be located outside of the focal plane of the reduction lens to avoid transfer of the images of the conductive lines onto the target semiconductor substrate during the mask pattern transfer process.

6569584, May 27, 2003

Jun 29, 2001

09/895538

Jonathan J. Ho - Fremont CA
Xin X. Wu - Fremont CA

Xilinx, Inc. - San Jose CA

G03F 900

430 5

A reticle (mask) that is modified to prevent bridging of the masking material (e. g. , chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.

6868537, Mar 15, 2005

Feb 25, 2002

10/082991

Jonathan J. Ho - Fremont CA, US
Xin X. Wu - Fremont CA, US
Zicheng Gary Ling - San Jose CA, US
Jan L. de Jong - Cupertino CA, US

Xilinx, Inc. - San Jose CA

G06F017/50

716 19, 716 20, 716 21

For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

7737020, Jun 15, 2010

Dec 21, 2005

11/313521

Jonathan Jung-Ching Ho - Fremont CA, US

XILINX, Inc. - San Jose CA

H01L 21/4763

438619, 257522, 257E21573

Fluid-based dielectric material is used to backfill multiple patterned metal layers of an IC on a wafer. The patterned metal layers are fabricated using conventional CMOS techniques, and are IMD layers in particular embodiments. The dielectric material(s) are etched out of the IC to form a metal network, and fluid dielectric material precursor, such as a polyarylene ether-based resin, is applied to the wafer to backfill the metal network with low-k fluid-based dielectric material.

7765498, Jul 27, 2010

May 24, 2007

11/805739

Jonathan J. Ho - Fremont CA, US
Yan Wang - Campbell CA, US
Xin X. Wu - Fremont CA, US
Jane W. Sowards - Fremont CA, US

XILINX, Inc. - San Jose CA

G06F 17/50

716 3, 716 7, 716 11

Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e. g. , transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e. g. , transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.

7951722, May 31, 2011

Aug 8, 2007

11/891258

Jonathan Jung-Ching Ho - Fremont CA, US

Xilinx, Inc. - San Jose CA

H01L 21/302
C23F 1/00

438719, 438706, 216 41, 216 58

A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

8384164, Feb 26, 2013

May 3, 2011

13/099698

Jonathan Jung-Ching Ho - Fremont CA, US

Xilinx, Inc. - San Jose CA

H01L 27/088

257401, 257412

An interconnect structure includes a substrate, a first diffusion region within the substrate, a plurality of first lines on the substrate and the first diffusion region, a first enclosure coupled to an end of the plurality of first lines, and a first contact within the first enclosure. The interconnect structure further includes a second diffusion region within the substrate, a plurality of second lines on the substrate and the second diffusion region, a second enclosure coupled to an end of the plurality of second lines, and a second contact within the second enclosure. A spacing can be present between the plurality of first lines and the plurality of second lines. The plurality of first lines, the first contact, the plurality of second lines, and the second contact are trimmed, but the first enclosure, the second enclosure, and the spacing are not trimmed.

20230067841, Mar 2, 2023

Aug 2, 2021

17/391150

- Mountain View CA, US
Jonathan Ho - Berkeley CA, US
William Chan - Toronto, CA
Tim Salimans - Utrecht, NL
David Fleet - Toronto, CA
Mohammad Norouzi - Toronto, CA

G06T 5/00
G06T 5/50
G06T 3/40
G06N 3/08
G06N 3/04

A method includes receiving, by a computing device, training data comprising a plurality of pairs of images, wherein each pair comprises an image and at least one corresponding target version of the image. The method also includes training a neural network based on the training data to predict an enhanced version of an input image, wherein the training of the neural network comprises applying a forward Gaussian diffusion process that adds Gaussian noise to the at least one corresponding target version of each of the plurality of pairs of images to enable iterative denoising of the input image, wherein the iterative denoising is based on a reverse Markov chain associated with the forward Gaussian diffusion process. The method additionally includes outputting the trained neural network.