Aram H Mkhitarian

20090309155, Dec 17, 2009

Jun 12, 2008

12/138273

Aram H. Mkhitarian - Glendale CA, US

H01L 49/00
H01L 21/76

257327, 438439, 257E49001, 257E2154

A vertical transistor with integrated isolation is provided. The vertical transistor includes a vertical semiconductor structure and an isolation layer on a bottom surface of the vertical semiconductor structure. The vertical transistor further includes a plurality of terminals on a top surface of the vertical semiconductor structure.

62975331, Oct 2, 2001

Apr 30, 1998

9/070048

Aram Mkhitarian - Glendale CA

The Whitaker Corporation - Wilmington DE

H01L 27088

257336

A lateral conduction MOS structure characterized by reduced source resistance and reduced pitch. The structure includes a semiconductor substrate having an epitaxial semiconductor layer thereon, the substrate and epitaxial layer being of the same conductivity type. The structure further includes a source layer and a drain layer, each layer being of a second conductivity type, and a channel layer disposed between the source layer and the drain layer. The channel layer has an oxide layer and a gate disposed thereon. At least one of a wet anisotropic and a reactive ion etching step is performed to define a trench having a maximum width of about from 4-6 microns and a depth that extends well into the substrate. An electrically conductive via is then formed by deposition of metal into the trench to thereby establish a low resistance path between the source and the substrate ground.