Anh Yen Ly

20040218422, Nov 4, 2004

May 2, 2003

10/428742

Hung Nguyen - Fremont CA, US
Sang Nguyen - Union City CA, US
Elbert Lin - Fremont CA, US
Anh Ly - San Jose CA, US

G11C011/34

365/185210

A non-volatile memory semiconductor device has a circuit to compensate for the variation in the data pattern to be programmed. The variation in the data patter creates a variation in the current requirement. The array receives a plurality of data pattern signals which affect the total amount of current flowing into a plurality of columns and into the memory array. A high voltage source generates an output which is supplied along a conducting path connected to the group of columns. A pass transistor is in the conducting path controlling the current flow in the conducting path. A current source has a first terminal and a second terminal with the first terminal connected to the output of the high voltage generator and the second terminal connected to the gate of the pass transistor. A plurality of current sources are collectively connected to a node. Each of the plurality of current sources receives a plurality of second signals with each second signal being an inverse of the first signal, and controlling the total amount of current flowing through the node. A current mirror circuit is connected to the node and to the gate of the pass transistor and controls the pass transistor in response to the amount of current flowing through the node.

20160141034, May 19, 2016

Jan 22, 2016

15/003811

- San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Thuan Vu - San Jose CA, US

G11C 16/08

Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

20150255165, Sep 10, 2015

Mar 4, 2014

14/196839

- San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Thuan Vu - San Jose CA, US

Silicon Storage Technology, Inc. - San Jose CA

G11C 16/28

Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.

20150003166, Jan 1, 2015

Aug 1, 2014

14/449926

- San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Thuan Vu - San Jose CA, US

G11C 16/10
G11C 16/26
H01L 27/115

36518518

A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.