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Anh P Ly

from Elk Grove, CA
Age ~59
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Also known as:
Anh Dao Ly, Anh P Dao
Related to:
Sang Pom Lee, 83Wendy Nghiem Ly, 65Frederick S Ly, 60Andrew Ly, 28Justin S LyKhau D Ly, 87Ly C Hou, 80Shirley Ly, 32Sreng S Ly, 62Lien N Tu, 51Ngor S Ly, 76Amy Ly, 30
Connected to:
Amadou T Ly, 70Amber A Ly, 46Asia N Ly, 46Bora S Ly, 43Brannon D Ly, 53Bunlim Ly, 46Bunna N Ly, 69Bunthoeun Ly, 65Carole Ly, 54Caroline T Ly, 44

Anh Ly Phones & Addresses

  • Elk Grove, CA
  • Rancho Cordova, CA
  • 29269 States St, Hayward, CA 94544 (510) 782-8174
  • San Francisco, CA
  • Sacramento, CA

Professional Records

License Records

Anh Thi Ly

License #:
1206007938
Category:
Nail Technician License

Anh Ngoc Ly

License #:
1206015299
Category:
Nail Technician License

Medicine Doctors

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Anh Ly

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Specialties:
General Surgery
Work:
Better Health Medical Group
116 W Lime Ave, Monrovia, CA 91016
(626) 599-8323 (phone), (626) 768-7459 (fax)
Languages:
English
Description:
Ms. Ly works in Monrovia, CA and specializes in General Surgery. Ms. Ly is affiliated with Methodist Hospital Of Southern California.

Resumes

Resumes

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Caregiver

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Work:
Ihss Public Authority
Caregiver
Education:
Santa Ana College
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Anh Ly

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Location:
Elk Grove, CA
Work:
Cosumnes River College
Student
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Anh Ly

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Anh Ly

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Anh Ly

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Caregiver

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Work:
Ihss Public Authority
Caregiver
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Anh Ly

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Industry:
Aviation & Aerospace
Anh Ly Photo 9

Entrepreneur

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Position:
Business Developer at SimpLyTeas.com
Location:
Sacramento, California Area
Industry:
Banking
Work:
SimpLyTeas.com
Business Developer
Silicon Valley Bank Jan 2011 - Jun 2012
Relationship Advisor with Entrepreneur Banking Services
BUILD 2006 - 2011
Mentor
Silicon Valley Bank Jan 2009 - Dec 2010
Relationship Advisor
Silicon Valley Bank Aug 2006 - Dec 2008
Client Service Advisor
Education:
California State University-Sacramento
Bachelor of Science in Business Administration, Concentration in Marketing
Skills:
Banking
Commercial Banking
Financial Analysis
Portfolio Management
Relationship Management
Financial Services
Cash Management
Interests:
Long distance running, reading, camping the old fashion way, traveling and getting stamps on my passport, up for any physical or mental challenge (Tough Mudder!), and trying all different types of ethnic food.
Certifications:
Property, Casualty, Life, Accident and Health, State of California
Series 6 and 63, FINRA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Anh Minh Ly
President
MODERN ADVANCED CERAMICS INC
Nonclassifiable Establishments
2240 Lundy Ave, San Jose, CA 95131
Anh Ly
Owner
Ly, Anh
Beauty Shop
3490 Mt Diablo Blvd, Lafayette, CA 94549
(925) 284-3850

Publications

Us Patents

Low Voltage Cmos Bandgap Reference

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US Patent:
6943617, Sep 13, 2005
Filed:
Dec 29, 2003
Appl. No.:
10/748540
Inventors:
Hieu Van Tran - San Jose CA, US
Tam Huu Tran - San Jose CA, US
Vishal Sarin - Santa Clara CA, US
Anh Ly - San Jose CA, US
Niang Hangzo - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G05F001/10
US Classification:
327539
Abstract:
A bandgap reference generator comprises a PMOS transistor and NMOS transistor in a pnp bipolar junction transistor connected in series in a first leg. The bandgap reference generator includes a second leg that includes a PMOS transistor, an NMOS transistor, a resistor and a pnp bipolar junction transistor. A bias circuit provides a bias to a mirror formed by the gates of the PMOS transistors to lower the operating voltage of the bandgap reference generator. A second biasing circuit may provide bias to the mirror formed of the NMOS transistors. A time-based and a DC bias-based start up circuitry and method is provided.

Multi-Operational Amplifier System

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US Patent:
7236054, Jun 26, 2007
Filed:
Jan 28, 2004
Appl. No.:
10/767248
Inventors:
Hieu Van Tran - San Jose CA, US
Anh Ly - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Vishal Sarin - Cupertino CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H03F 3/45
US Classification:
330253, 330 9, 330 51, 330 69, 330124 R, 330147, 330285, 330295, 310311
Abstract:
A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

Multi-Operational Amplifier System

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US Patent:
7276971, Oct 2, 2007
Filed:
Jan 11, 2007
Appl. No.:
11/652719
Inventors:
Hieu Van Tran - San Jose CA, US
Anh Ly - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Vishal Sarin - Cupertino CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H03F 3/45
US Classification:
330253, 330 9, 330 51, 330124 R, 330147, 330285, 330295
Abstract:
A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

Test Circuit And Method For Multilevel Cell Flash Memory

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US Patent:
7325177, Jan 29, 2008
Filed:
Nov 17, 2004
Appl. No.:
10/991702
Inventors:
Hieu Van Tran - San Jose CA, US
Anh Ly - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Vishal Sarin - Cupertino CA, US
Hung Q. Nguyen - Fremont CA, US
William John Saiki - Mountain View CA, US
Loc B. Hoang - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
A test circuit is sued to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

Multi-Operational Amplifier System

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US Patent:
7436258, Oct 14, 2008
Filed:
Jul 30, 2007
Appl. No.:
11/830720
Inventors:
Hieu Van Tran - San Jose CA, US
Anh Ly - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Vishal Sarin - Cupertino CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H03F 1/14
US Classification:
330 51, 330124 R, 330253, 330285, 330295
Abstract:
A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.

Method For Handling A Defective Top Gate Of A Source-Side Injection Flash Memory Array

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US Patent:
7447073, Nov 4, 2008
Filed:
Feb 16, 2007
Appl. No.:
11/707341
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/34
US Classification:
36518515, 36518514, 36518509, 36518522, 36518518, 36518529
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash Memory Array Having Control/Decode Circuitry For Disabling Top Gates Of Defective Memory Cells

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US Patent:
7567458, Jul 28, 2009
Filed:
Sep 26, 2005
Appl. No.:
11/235901
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/34
US Classification:
36518515, 36518514, 36518509, 36518511, 36518503, 36518523
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Flash Memory Array System Including A Top Gate Memory Cell

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US Patent:
7626863, Dec 1, 2009
Filed:
Feb 16, 2007
Appl. No.:
11/707343
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Anh Ly - San Jose CA, US
Sheng-Hsiung Hsueh - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US
Loc B. Hoang - San Jose CA, US
Steve Choi - Irvine CA, US
Thuan T. Vu - San Jose CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/04
US Classification:
36518515, 36518514, 36518503
Abstract:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
Control profile
Anh P Ly from Elk Grove, CA, age ~59 Get Report