Andy Quang Lee

6335634, Jan 1, 2002

May 22, 2000

09/577297

Srinivas T. Reddy - Fremont CA, 94539
Ketan Zaveri - San Jose CA, 95129
Christopher F. Lane - Campbell CA, 95008
Andy L. Lee - San Jose CA, 95131
Cameron R. McClintock - Mountain View CA, 94043
Bruce B. Pedersen - San Jose CA, 95136
Manuel Mejia - San Jose CA, 95116
Richard G. Cliff - Milpitas CA, 95116

G06F 738

326 41, 326 40, 326 39, 326 38

Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

6344755, Feb 5, 2002

Oct 18, 2000

09/691424

Srinivas T. Reddy - Fremont CA
Manuel Mejia - San Jose CA
Andy L. Lee - San Jose CA
Bruce B. Pedersen - San Jose CA

Altera Corporation - San Jose CA

H03K 19003

326 10, 326 38, 326 39

A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows.

6353551, Mar 5, 2002

Nov 19, 1999

09/443940

Andy Lee - San Jose CA

Altera Corporation - San Jose CA

G11C 1100

365154, 365205, 36518908

A static random access memory (âSRAMâ) that is especially suitable for such uses as inclusion on a programmable logic device to provide programmable control of the configuration of that device. The SRAM includes a plurality of SRAM cells, all of which are simultaneously cleared to a first of two logic states by application of a second of the two logic states to clear terminals of the cells. Any cell that needs to be programmed to the second of the two logic states is thereafter specifically addressed and a data signal thereby applied which programs the cell to the second logic state. The cells are preferably constructed so that they are programmed to the second logic state by application of a data signal having the first logic state. Even a very small unipolar MOS pass gate transistor can therefore be used as the addressable path through which the data signal is applied. The memory may also include circuitry for verifying the contents of each cell via the data input terminal of the cell.

6384625, May 7, 2002

Mar 30, 2001

09/823603

Andy L. Lee - San Jose CA
Christopher F. Lane - Campbell CA
Bruce B. Pedersen - San Jose CA

Altera Corporation - San Jose CA

G06F 738

326 38, 326 39, 326 41

Programmable logic modules on a programmable logic device each include a four-input look-up table circuit which can be programmed to allow the logic module to produce an output signal which can be any of a plurality of logical combinations of four input signals applied to the logic module. In addition, each logic module is augmented with additional circuitry that allows the logic module to be alternatively operated as a dynamic four-to-one multiplexer.

6411124, Jun 25, 2002

Jan 16, 2001

09/761602

Andy L. Lee - San Jose CA
Brian Johnson - Sunnyvale CA
Richard G. Cliff - Los Altos CA

Altera Corporation - San Jose CA

H03K 19177

326 41, 326101

A logic module for a programmable logic device includes shift register circuitry in addition to the conventional programmable memory cells and look-up table decoder or selection control circuitry. In one embodiment the selection control circuitry can access either the memory cells or the various stages of the shift register. The shift register stages, and preferably the master and slave latches of each shift register stage, are accessed in a Gray code order. All of the stages of the shift register are preferably clearable in parallel. The shift registers of two logic modules are preferably cascadable to facilitate providing longer shift registers. Clock circuitry may be provided to facilitate providing two clock signals that are the logical inverse of one another with a common enable signal.

6417694, Jul 9, 2002

Sep 19, 2001

09/956748

Srinivas T. Reddy - Fremont CA
Richard G. Cliff - Milpitas CA
Christopher F. Lane - Campbell CA
Ketan H. Zaveri - San Jose CA
Manuel M. Mejia - San Jose CA
David Jefferson - San Jose CA
Bruce B. Pedersen - San Jose CA
Andy L. Lee - San Jose CA

Altera Corporation - San Jose CA

H03K 19177

326 41, 326 39

A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e. g.

6462577, Oct 8, 2002

Jan 16, 2001

09/761608

Andy L. Lee - San Jose CA
Christopher F. Lane - San Jose CA
Srinivas T. Reddy - Fremont CA
Brian D. Johnson - Sunnyvale CA
Ketan H. Zaveri - San Jose CA
Mario Guzman - San Jose CA
Quyen Doan - Milpitas CA

Altera Corporation - San Jose CA

H03K 19177

326 40, 326 47

A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.

6462597, Oct 8, 2002

Jan 31, 2000

09/494619

Andy L. Lee - San Jose CA

Altera Corporation - San Jose CA

H03H 1126

327261, 327108, 327112, 327263, 326 85, 326 87

Circuit techniques provide different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. Different circuit topologies are provided for delay chains on integrated circuits. Each implementation allows flexibility in delay elements through metal options to allow modifying delay chain delays with simple metal-only layout changes. Delay chains are used in integrated circuits to produce either a constant delay or to track another circuit delay.