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Amy Lee Yang

from Milwaukie, OR
Age ~61

Amy Yang Phones & Addresses

  • Milwaukie, OR
  • Damascus, OR
  • San Jose, CA
  • Canby, OR
  • San Francisco, CA

Professional Records

Medicine Doctors

Amy Yang Photo 1

Amy Yang

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Specialties:
Psychiatry
Work:
Amy Wang MD
3093 Sacramento St, San Francisco, CA 94115
(415) 562-4770 (phone), (415) 276-9023 (fax)
Education:
Medical School
Tulane University School of Medicine
Graduated: 2007
Procedures:
Psychiatric Diagnosis or Evaluation
Psychiatric Therapeutic Procedures
Conditions:
Anxiety Dissociative and Somatoform Disorders
Anxiety Phobic Disorders
Attention Deficit Disorder (ADD)
Bipolar Disorder
Depressive Disorders
Languages:
English
Description:
Dr. Yang graduated from the Tulane University School of Medicine in 2007. She works in San Francisco, CA and specializes in Psychiatry.
Amy Yang Photo 2

Amy Yang

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Specialties:
Psychiatry
Education:
Tulane University (2007)
Butler Hospital (2011) *
Columbia University (2012) *
Amy Yang Photo 3

Amy Yang

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Specialties:
Psychiatry

License Records

Amy Yi-Pei Yang Md

License #:
26977 - Expired
Category:
Medicine
Issued Date:
Oct 2, 2012
Effective Date:
Aug 6, 2014
Expiration Date:
Oct 1, 2014
Type:
Physician

Resumes

Resumes

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Amy Yang San Jose, CA

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Work:
Polaronyxlaser

Dec 2013 to 2000
Fiber Laser Technician

Bizcom Electronics

May 2013 to Dec 2013
QA Tech / Assembler

Macy's - Valley Fair Mall
San Jose, CA
Nov 2012 to Nov 2012
Season Worker

Sheraton Hotel- Ho Chi Minh City

2004 to 2008
Front Desk & Cashier

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Amy Yang

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Work:
OpenTV

2003 to 2000
Technical Lead

ESS Technology
Fremont, CA
2002 to 2003
Software Engineer

Philips Semiconductor
Sunnyvale, CA
2002 to 2002
Sr. Software Engineer

DIVA Systems
Redwood City, CA
2000 to 2002
Software Engineer

Hyundai Electronics USA
San Jose, CA
1994 to 1998
Software Engineer

Education:
Ewha University
Seoul, KR
1990 to 1993
Bachelor of Science in Computer Science

Amy Yang Photo 6

Amy Yang San Jose, CA

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Work:
Pacific States Industries, Inc

Jul 2011 to Present
Staff Accountant

Sunnet Systems, Inc
Sunnyvale, CA
Feb 2011 to Jun 2011
Staff Accountant

AllBright Law Offices

Jul 2002 to Jul 2003
Legal Assistant

Education:
San Jose State University
San Jose, CA
Jan 2004 to Jan 2008
B.S. in double major of Accounting and Finance

East China University of Political Science and Law
Jun 2002
B.A. in Economic Law

Skills:
Oracle software, QuickBooks, Peachtree software and Microsoft Office Software (Excel, Power Point, Word)
Amy Yang Photo 7

Amy Y. Yang San Mateo, CA

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Work:
Seneschal Group Pte. Ltd

Jan 2011 to Present
Consultant / Advisor

Portston, Inc
San Mateo, CA
Aug 2007 to Dec 2010
Accounting Consultant

Hemming Morse CPA, Inc
San Francisco, CA
Aug 2004 to Jul 2007
Senior Financial Auditor

Hemming Morse CPA, Inc
San Francisco, CA
Aug 2004 to Jun 2005
Compliance Staff Auditor

MedAmerica, Inc
Oakland, CA
Sep 2001 to Jun 2003
Finance Intern

Education:
University of California at Berkeley
1999 to 2004
Bachelor of Arts

Business Records

Name / Title
Company / Classification
Phones & Addresses
Amy Yang
Director
Senior Aegis Communities LLC
Home Health Care Services Skilled Nursing Care Facility · Skilled Nursing Care Facility
36281 Fremont Blvd, Fremont, CA 94536
(510) 739-0909
Amy Yang
Shanghai Pool, L.P
3000 Sand Hl Rd, Menlo Park, CA 94025
Amy Yang
STANFORD PROFESSIONAL REALTY, INC
Real Estate Agent/Manager
4062 Fabian Way, Palo Alto, CA 94303
(650) 855-9999, (650) 855-9988
Amy Yang
Owner, President, Secretary
DIAMOND REALTY, INC
Real Estate Agent/Manager · Real Estate Agents
PO Box 230146, Portland, OR 97281
12385 SW Allen Blvd, Beaverton, OR 97005
(503) 646-6769
Amy Yang
Senior Quality Assurance Engineer
Geeknet
Retail · Online Media Publisher/ Advertising · Online Retailer · Online Retailer and Social Media Website
11216 Waples Ml Rd SUITE 100, Fairfax, VA 22030
650 Castro St, Mountain View, CA 94041
(650) 694-2100

Publications

Us Patents

(Design Rule Check)/(Electrical Rule Check) Algorithms Using A System Resolution

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US Patent:
6735749, May 11, 2004
Filed:
Mar 21, 2002
Appl. No.:
10/103521
Inventors:
Mu-Jing Li - Sunnyvale CA
Amy Yang - Saratoga CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 1750
US Classification:
716 5, 703 1, 716 2, 716 11
Abstract:
Method and apparatus for checking integrated circuit designs. In particular, one embodiment of the present invention is a method that for checking integrated circuit design files using (design rule check)/(electrical rule check) files (DRC/ERC files) wherein design objects are disposed on a grid having a system resolution, the method comprising steps of: (a) growing one or more rectangular boxes having at least two sides of length equal to the system resolution outward or inward from one or more of an edge of a design object and a side of a design object; (b) performing one or more of a spacing DRC/ERC check and an overlay DRC/ERC check; and (c) identifying checks relating to the rectangular boxes.

Method To Simplify And Speed Up Design Rule/Electrical Rule Checks

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US Patent:
6769099, Jul 27, 2004
Filed:
Apr 12, 2002
Appl. No.:
10/121322
Inventors:
Mu-Jing Li - Sunnyvale CA
Amy Yang - Saratoga CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 1750
US Classification:
716 2, 716 4
Abstract:
A method, apparatus and computer program product for checking of integrated circuit design files using rules files. Each of the rules files has a rule associated therewith. The rules are sequentially compared with objects associated with the design files in an object-to-check-pool (OTCP). The sequence in which the rules are compared to objects in the OTCP is arrange to maximize a probability of determining whether design characteristics of the objects in the OTCP satisfies all rules associated with the rules files while minimizing a number of rules that must be compared with the OTCP.

Redundant Via Rule Check In A Multi-Wide Object Class Design Layout

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US Patent:
6804808, Oct 12, 2004
Filed:
Sep 30, 2002
Appl. No.:
10/260817
Inventors:
Mu-Jing Li - Sunnyvale CA
Amy Yang - Saratoga CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 1750
US Classification:
716 5, 716 4
Abstract:
A redundant via design rule check is preferably performed on multi-wide object class design layouts to ensure that each connection area between two conductive layers has at least a certain number of vias and/or has vias placed appropriately to reduce the risk of via failure due to vacancy concentration of isolated vias. In exemplary embodiments, a redundant via design rule check preferably ensures that for vias placed within a connection area of a metal feature (or within a localized region of a larger metal geometry) that is both greater than a certain width and greater than a certain area in size, the vias are both sufficient in number and/or suitable in their location. Vias located inside a geometry but falling outside a virtual edge of a wide class object may be included to satisfy exemplary rules.

Structure And Method For Separating Geometries In A Design Layout Into Multi-Wide Object Classes

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US Patent:
6871332, Mar 22, 2005
Filed:
Sep 30, 2002
Appl. No.:
10/260813
Inventors:
Mu-Jing Li - Sunnyvale CA, US
Amy Yang - Saratoga CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F017/50
US Classification:
716 5, 716 2
Abstract:
Manipulation of a multi-wide object class design layout to facilitate design rule checking or automatic correction of design rule errors is improved by deriving wide class objects from geometries of the design layout, and applying certain rules to non-virtual boundaries of the wide class objects that are not applied to virtual boundaries of the wide class objects. In an exemplary embodiment, the wide class objects are preferably derived by sizing down, then sizing up, each geometry by a sizing factor equal to half the minimum width of the particular wide class object less an amount that preferably corresponds to that represented by a minimum resolution of the design layout. Portions of a geometry that are otherwise excluded as being too narrow in width, but that lie wholly within a correction factor of the boundary of the wide class object otherwise derived, are preferably included to form effective wide class objects.

Via Enclosure Rule Check In A Multi-Wide Object Class Design Layout

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US Patent:
6883149, Apr 19, 2005
Filed:
Sep 30, 2002
Appl. No.:
10/260811
Inventors:
Mu-Jing Li - Sunnyvale CA, US
Amy Yang - Saratoga CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F017/50
US Classification:
716 4, 716 1, 716 5, 716 6, 716 8, 716 10, 716 12, 716 14
Abstract:
In a multi-wide class design layout, design rule checks for enclosure of multi wide class objects prevent false errors or false passes by performing such checks against the non-virtual boundaries of a wide class object, and not against the virtual boundaries. An exemplary embodiment provides a method for identifying as a violation, for each wide class wobject, any geometry on another layer which is located at least partially inside the wobject and has any portion thereof located within a distance enclof any non-virtual boundary of the wobject. The exemplary method is preferably performed using effective wide class objects.

Patching Technique For Correction Of Minimum Area And Jog Design Rule Violations

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US Patent:
6892368, May 10, 2005
Filed:
Feb 26, 2003
Appl. No.:
10/374948
Inventors:
Mu-Jing Li - Sunnyvale CA, US
Amy Yang - Saratoga CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F017/50
US Classification:
716 5, 716 4
Abstract:
Automated patching techniques to correct certain rule violations are used, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit. A series of patches of predefined orientations are utilized to correct design rule violations. A set of violations are identified, patches of a predefined orientation are attempted to correct one or more violations. Patches of another predefined orientation are attempted to correct remaining violations. Attempted patching is repeated until all patches in the series have been attempted or all violations have been corrected. Patches can be added to a construction layer over the set of violations, and each patch that does not cause a design rule violation can be copied to a metal layer. A series of patches of predefined orientations are used, efficiently correcting design rule violations such as minimum area and jog rule violations.

Multimedia Stream Incorporating Interactive Support For Multiple Types Of Subscriber Terminals

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US Patent:
6578201, Jun 10, 2003
Filed:
Nov 20, 1998
Appl. No.:
09/197270
Inventors:
Tobie J. LaRocca - San Jose CA
Amy Yang - San Jose CA
Gregory A. Erickson - San Francisco CA
Assignee:
Diva Systems Corporation - Redwood City CA
International Classification:
H04N 7173
US Classification:
725 86, 725 61, 725135, 725140, 709201, 709231
Abstract:
A multimedia stream incorporating interactive support for multiple types of subscriber terminals. The multimedia stream is created by multiplexing several component streams. The component streams include a video stream, an audio stream, and an interactive data stream. The interactive data stream includes data specific to different types of subscriber terminals multiplexed together.
Amy Lee Yang from Milwaukie, OR, age ~61 Get Report