Albert X Wu

6518733, Feb 11, 2003

Aug 3, 2001

09/921466

Jeffrey Schenkel - Burlington MA
Albert M. Wu - Sunnyvale CA
Robert C. Dobkin - Monte Sereno CA
Steven M. Pietkiewicz - Fremont CA

Linear Technology Corporation - Milpitas CA

H02J 700

320166

The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

6636021, Oct 21, 2003

Dec 18, 2002

10/324628

Jeffrey Schenkel - Burlington MA, 01803
Albert M. Wu - Sunnyvale CA, 94087
Robert C. Dobkin - Monte Sereno CA, 95030
Steven M. Pietkiewicz - Fremont CA, 94539

H02J 714

320166

The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

6876031, Apr 5, 2005

Feb 23, 1999

09/256265

Dah-Bin Kao - Palo Alto CA, US
Loc B. Hoang - San Jose CA, US
Albert T. Wu - Palo Alto CA, US

Winbond Electronics Corporation - Hsin chu

H01L029/788
G11C016/04

257315, 257317, 36518501, 36518526, 36518529

A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

6940107, Sep 6, 2005

Dec 12, 2003

10/734779

Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US

Marvell International Ltd. - Hamilton

H01L027/10

257209, 257529, 257530

A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

7288845, Oct 30, 2007

May 8, 2003

10/434524

Sehat Sutardja - Los Altos Hills CA, US
Albert Wu - Palo Alto CA, US
Jin-Yuan Lee - Hsin-chu, TW
Mou-Shiung Lin - Hsin-chu, TW

Marvell Semiconductor, Inc. - Sunnyvale CA
MEGIC Corporation - Hsinchu

H01L 23/485

257781, 257786, 257784, 257E2302

A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

7292005, Nov 6, 2007

Feb 3, 2006

11/347791

Steven M Pietkiewicz - Fremont CA, US
Albert M Wu - Sunnyvale CA, US

Linear Technology Corp. - Milpitas CA

H01M 10/44
H01M 10/46

320166

The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

7344924, Mar 18, 2008

May 24, 2005

11/136925

Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US

Marvell International Ltd. - Hamilton

H01L 21/82

438129, 438132, 438215, 257209

A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

7359261, Apr 15, 2008

Feb 7, 2006

11/349460

Albert Wu - Palo Alto CA, US
Sehat Sutardja - Los Altos CA, US

Marvell International Ltd. - Hamilton

G11C 7/00

365200, 365201, 36523006

An IC includes a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module communicates with the memory module and the memory repair database, detects defective memory locations in the memory module, locates redundant memory elements in the memory module, stores information that associates memory addresses of the defective memory locations with the redundant memory elements in the memory repair database, and outputs the information. The memory control module includes a plurality of electrical fuses. Storing the information includes electrically altering at least one of the plurality of electrical fuses. A redundant memory decoder module receives the information and physically remaps the memory addresses to the redundant memory locations.