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Yasunari Kanzawa

from Cupertino, CA
Age ~54
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Related to:
Aki Kanzawa
Connected to:
David M Kanze, 46Jonathan S Kanze, 49Randall E Kanzig, 68Peggy A Kanzigg, 79Charles G Kanzinger, 52Mary A Kanzius, 76Audrey A Kanzler, 78Barbara J Kanzler, 61Christine Kanzler, 65Darlene C Kanzler, 56

Yasunari Kanzawa Phones & Addresses

  • Cupertino, CA
  • Sunnyvale, CA

Work

Company: Synopsys, inc. 2007 Position: Senior staff corporate application engineer

Skills

Eda • Testing • Asic • Perl • Test Automation • Semiconductors • Electronics

Languages

English • Japanese

Industries

Computer Software

Resumes

Resumes

Yasunari Kanzawa Photo 1

Senior Staff Corporate Application Engineer

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
Synopsys, Inc. since 2007
Senior Staff Corporate Application Engineer
Nihon Synopsys Co., Ltd. 1999 - 2007
Staff Application Consultant
Oki Electric Industry Co., Ltd. 1992 - 1999
Senior Engineer
Skills:
Eda
Testing
Asic
Perl
Test Automation
Semiconductors
Electronics
Languages:
English
Japanese

Publications

Us Patents

Implementing Hierarchical Design-For-Test Logic For Modular Circuit Design

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US Patent:
8065651, Nov 22, 2011
Filed:
Jan 29, 2009
Appl. No.:
12/362284
Inventors:
Rohit Kapur - Cupertino CA, US
Anshuman Chandra - Mountain View CA, US
Yasunari Kanzawa - Sunnyvale CA, US
Jyotirmoy Saikia - Bangalore, IN
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716136, 716106, 714724
Abstract:
Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.

Increasing Scan Compression By Using X-Chains

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US Patent:
20100083199, Apr 1, 2010
Filed:
Sep 30, 2008
Appl. No.:
12/242573
Inventors:
Peter Wohl - Williston VT, US
John A. Waicukauski - Tualatin OR, US
Frederic J. Neuveux - Meylan, FR
Yasunari Kanzawa - Sunnyvale CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G01R 31/28
US Classification:
716 4, 714726
Abstract:
To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
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Yasunari Kanzawa from Cupertino, CA, age ~54 Get Report