Stavros Kalafatis

6374350, Apr 16, 2002

Jun 1, 2000

09/584890

Reynold V. DSa - Portland OR
Rebecca E. Hebda - Sherwood OR
Stavros Kalafatis - Portland OR
Alan B. Kyker - Davis OR
Robert B. Chaput - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 942

712239, 712202, 712238

An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

6535905, Mar 18, 2003

Apr 29, 1999

09/302633

Stavros Kalafatis - Portland OR
Alan B. Kyker - Potland OR
Robert D. Fisch - Portland OR

Intel Corporation - Santa Clara CA

G06F 900

709108, 709103, 712219, 712228

A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.

6785890, Aug 31, 2004

Sep 20, 2002

10/251527

Stavros Kalafatis - Portland OR
Alan B. Kyker - Potland OR
Robert D. Fisch - Portland OR

Intel Corporation - Santa Clara CA

G06F 1500

718108, 718103, 712219, 712228

A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.

6795845, Sep 21, 2004

Sep 20, 2002

10/251204

Stavros Kalafatis - Portland OR
Alan B. Kyker - Potland OR
Robert D. Fisch - Portland OR

Intel Corporation - Santa Clara CA

G06F 900

709108, 709103, 712228, 712219

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A branch instruction within the instruction information of the first thread to be dispatched from the instruction information source is also detected. Responsive to the detection of the branch instruction and the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.

6850961, Feb 1, 2005

Sep 20, 2002

10/251583

Stavros Kalafatis - Portland OR,
Alan B. Kyker - Potland OR,
Robert D. Fisch - Portland OR,

Intel Corporation - Santa Clara CA

G06R 960

709108, 712228, 712219

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A stall condition relating to the first thread within a processor pipeline of the multithreaded processor is detected. The elapsing of a predetermined time interval subsequent to the detection of the stall condition is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread and the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.

6854118, Feb 8, 2005

Sep 20, 2002

10/251599

Stavros Kalafatis - Portland OR,
Alan B. Kyker - Potland OR,
Robert D. Fisch - Portland OR,

Intel Corporation - Santa Clara CA

G06F009/00

718108, 718103, 712219, 712228

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.

6865740, Mar 8, 2005

Sep 20, 2002

10/248000

Stavros Kalafatis - Portland OR,
Alan B. Kyker - Portland OR,
Robert D. Fisch - Portland OR,

Intel Corporation - Santa Clara CA

G06F009/00

718108, 718103, 712219, 712228

A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.

6971104, Nov 29, 2005

Sep 20, 2002

10/251508

Stavros Kalafatis - Portland OR,
Alan B. Kyker - Potland OR,
Robert D. Fisch - Portland OR,

Intel Corporation - Santa Clara CA

G06F009/00

718108, 718103, 712219, 712228

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.