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Stavros Kalafatis

from College Station, TX
Age ~57
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Also known as:
Mary Kalafatis, Stavros Kalatatis, Kalafatis Stavros
Related to:
Jack Blesma, 87Mary E Chile, 78Derick Williams, 39
Connected to:
Dimitrios G Kalafatis, 51Eleni M Kalafatis, 35Nick K Kalafatis, 42Susan C Kalafatis, 57Tammy L Kalafatis, 55Joshua Kalafchi, 39Andrea Kalafut, 42Gabor Kalafut, 43Kevin Kalafut, 34Thomas M Kalafut, 55

Stavros Kalafatis Phones & Addresses

  • College Station, TX
  • San Francisco, CA
  • Denver, CO
  • Pacific City, OR
  • 12514 Brimpton Ct, Portland, OR 97229
  • 19869 Logie Trail Rd, Portland, OR 97231
  • Bend, OR
  • Hawi, HI
  • Hillsboro, OR
  • 12514 NW Brimpton Ct, Portland, OR 97229 (503) 780-7210

Work

Company: Texas a&m university Mar 2019 Position: Associate department head

Education

Degree: Masters School / High School: University of Arizona 1989 to 1991 Specialities: Electronics Engineering

Skills

Semiconductors • Microprocessors • Soc • Asic • Processors • Intel • Ic • Verilog • Vlsi • Debugging • Computer Architecture • Physical Design • Hardware Architecture • Program Management • Integrated Circuit Design • Mixed Signal • Eda • Cmos • Low Power Design • Embedded Systems • Engineering Management • Circuit Design • Cross Functional Team Leadership • Analog • Silicon • Simulations • Fpga • Perl • Semiconductor Industry • Power Management • Management • Product Marketing • Rtl Design • Static Timing Analysis • Product Management • Leadership • System Architecture • Product Development • Storage • Go To Market Strategy • Strategic Partnerships • Business Development • Customer Relations • Team Building • Teaching • Presentations • Mentoring • Relationship Building

Interests

Social Services • Children • Economic Empowerment • Education • Environment • Poverty Alleviation • Science and Technology • Disaster and Humanitarian Relief • Human Rights • Health

Emails

s***[email protected]

Industries

Higher Education

Resumes

Resumes

Stavros Kalafatis Photo 1

Associate Department Head

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Location:
5013 Commonwealth Ct, College Station, TX 77845
Industry:
Higher Education
Work:
Texas A&M University
Associate Department Head
Texas A&M University Feb 2016 - Feb 2018
Professor
Texas A&M University Feb 2016 - Feb 2018
Professor of the Electrical and Electronic Engineering Practice
Teaxas A&M University Feb 2016 - Feb 2018
Professor of the Electrical and Electronic Engineering Practice
Nnmi 2016 - 2016
Industry Outreach
Education:
University of Arizona 1989 - 1991
Masters, Electronics Engineering The American College of Greece 1972 - 1978
Skills:
Semiconductors
Microprocessors
Soc
Asic
Processors
Intel
Ic
Verilog
Vlsi
Debugging
Computer Architecture
Physical Design
Hardware Architecture
Program Management
Integrated Circuit Design
Mixed Signal
Eda
Cmos
Low Power Design
Embedded Systems
Engineering Management
Circuit Design
Cross Functional Team Leadership
Analog
Silicon
Simulations
Fpga
Perl
Semiconductor Industry
Power Management
Management
Product Marketing
Rtl Design
Static Timing Analysis
Product Management
Leadership
System Architecture
Product Development
Storage
Go To Market Strategy
Strategic Partnerships
Business Development
Customer Relations
Team Building
Teaching
Presentations
Mentoring
Relationship Building
Interests:
Social Services
Children
Economic Empowerment
Education
Environment
Poverty Alleviation
Science and Technology
Disaster and Humanitarian Relief
Human Rights
Health

Publications

Us Patents

System And Method Of Maintaining And Utilizing Multiple Return Stack Buffers

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US Patent:
6374350, Apr 16, 2002
Filed:
Jun 1, 2000
Appl. No.:
09/584890
Inventors:
Reynold V. DSa - Portland OR
Rebecca E. Hebda - Sherwood OR
Stavros Kalafatis - Portland OR
Alan B. Kyker - Davis OR
Robert B. Chaput - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 942
US Classification:
712239, 712202, 712238
Abstract:
An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

Method And Apparatus For Thread Switching Within A Multithreaded Processor

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US Patent:
6535905, Mar 18, 2003
Filed:
Apr 29, 1999
Appl. No.:
09/302633
Inventors:
Stavros Kalafatis - Portland OR
Alan B. Kyker - Potland OR
Robert D. Fisch - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 900
US Classification:
709108, 709103, 712219, 712228
Abstract:
A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.

Method And System To Perform A Thread Switching Operation Within A Multithreaded Processor Based On Detection Of The Absence Of A Flow Of Instruction Information For A Thread

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US Patent:
6785890, Aug 31, 2004
Filed:
Sep 20, 2002
Appl. No.:
10/251527
Inventors:
Stavros Kalafatis - Portland OR
Alan B. Kyker - Potland OR
Robert D. Fisch - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1500
US Classification:
718108, 718103, 712219, 712228
Abstract:
A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.

Method And System To Perform A Thread Switching Operation Within A Multithreaded Processor Based On Detection Of A Branch Instruction

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US Patent:
6795845, Sep 21, 2004
Filed:
Sep 20, 2002
Appl. No.:
10/251204
Inventors:
Stavros Kalafatis - Portland OR
Alan B. Kyker - Potland OR
Robert D. Fisch - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 900
US Classification:
709108, 709103, 712228, 712219
Abstract:
A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A branch instruction within the instruction information of the first thread to be dispatched from the instruction information source is also detected. Responsive to the detection of the branch instruction and the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.

Method And System To Perform A Thread Switching Operation Within A Multithreaded Processor Based On Detection Of A Stall Condition

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US Patent:
6850961, Feb 1, 2005
Filed:
Sep 20, 2002
Appl. No.:
10/251583
Inventors:
Stavros Kalafatis - Portland OR, US
Alan B. Kyker - Potland OR, US
Robert D. Fisch - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06R 960
US Classification:
709108, 712228, 712219
Abstract:
A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A stall condition relating to the first thread within a processor pipeline of the multithreaded processor is detected. The elapsing of a predetermined time interval subsequent to the detection of the stall condition is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread and the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.

Method And System To Perform A Thread Switching Operation Within A Multithreaded Processor Based On Detection Of A Flow Marker Within An Instruction Information

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US Patent:
6854118, Feb 8, 2005
Filed:
Sep 20, 2002
Appl. No.:
10/251599
Inventors:
Stavros Kalafatis - Portland OR, US
Alan B. Kyker - Potland OR, US
Robert D. Fisch - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F009/00
US Classification:
718108, 718103, 712219, 712228
Abstract:
A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.

Method And System To Insert A Flow Marker Into An Instruction Stream To Indicate A Thread Switching Operation Within A Multithreaded Processor

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US Patent:
6865740, Mar 8, 2005
Filed:
Sep 20, 2002
Appl. No.:
10/248000
Inventors:
Stavros Kalafatis - Portland OR, US
Alan B. Kyker - Portland OR, US
Robert D. Fisch - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F009/00
US Classification:
718108, 718103, 712219, 712228
Abstract:
A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.

Method And System To Perform A Thread Switching Operation Within A Multithreaded Processor Based On Dispatch Of A Quantity Of Instruction Information For A Full Instruction

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US Patent:
6971104, Nov 29, 2005
Filed:
Sep 20, 2002
Appl. No.:
10/251508
Inventors:
Stavros Kalafatis - Portland OR, US
Alan B. Kyker - Potland OR, US
Robert D. Fisch - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F009/00
US Classification:
718108, 718103, 712219, 712228
Abstract:
A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.
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Stavros Kalafatis from College Station, TX, age ~57 Get Report