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Solomon I Beilin

from San Carlos, CA
Age ~89
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Also known as:
Solomon Betty Beilin, Harry R Beilin, Harry Ronald Beilin, Solomon Betty Beitin, Solomon I Beitin, Solomon I Beili, Eilim B Solomon
Phone and address:
83 Club Dr, San Carlos, CA 94070
(650) 598-9859
Related to:
Betty Beilin, 86Natasha Beilin, 50Harry R Beilin, 60
Connected to:
Ella Beilin, 85Leanna E Beilin, 53Lauren Beilinson, 39Vadim A Beilinson, 58Beau E Beilke, 33Brian R Beilke, 47Chris R Beilke, 65Christine M Beilke, 64Clare N Beilke, 38Dawn M Beilke, 54

Solomon Beilin Phones & Addresses

  • 83 Club Dr, San Carlos, CA 94070 (650) 598-9859 (650) 631-9500
  • 3366 La Mesa Dr, San Carlos, CA 94070
  • 119 Northam Ave, San Carlos, CA 94070
  • 1465 Drake Ave, Burlingame, CA 94010
  • Hillsborough, CA
  • Oakland, CA
  • San Mateo, CA
  • Newton Falls, OH

Publications

Us Patents

Systems Based On Opto-Electronic Substrates With Electrical And Optical Interconnections And Methods For Making

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US Patent:
6343171, Jan 29, 2002
Filed:
Apr 20, 1999
Appl. No.:
09/295813
Inventors:
Tetsuzo Yoshimura - Sunnyvale CA
Masaaki Inao - San Jose CA
Michael G. Lee - San Jose CA
William Chou - Cupertino CA
Solomon I. Beilin - San Carlos CA
Wen-chou Vincent Wang - Cupertino CA
James J. Roman - Sunnyvale CA
Thomas J. Massingill - Scotts Valley CA
Assignee:
Fujitsu Limited
International Classification:
G02B 626
US Classification:
385 50, 385 14, 385 18, 385 24
Abstract:
Opto-electrical systems having electrical and optical interconnections formed in thin layers with thin-film active devices are disclosed. In one embodiment, optical connections are made between the edge of one substrate and the surface of another substrate with the use of photorefractive materials. In another embodiment, the optical connection is made by separating a optical film from the first substrate and coupling the first substrate and the optical film to separate receptacles located on the second substrate. Film optical link modules employing aspects of the invention are also disclosed.

Methods For Fabricating Flexible Circuit Structures

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US Patent:
6391220, May 21, 2002
Filed:
Aug 18, 1999
Appl. No.:
09/376645
Inventors:
Lei Zhang - San Jose CA
Solomon Beilin - San Carlos CA
Som S. Swamy - Danville CA
James J. Roman - Sunnyvale CA
Assignee:
Fujitsu Limited, Inc.
International Classification:
B32B 3100
US Classification:
216 67, 438694, 438706, 438957, 438968, 438976, 29846, 29849, 156247, 156248, 1562739
Abstract:
Methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer on substrate, and then forming a conductive laminate on the release layer. After the release layer is formed, the conductive laminate can be easily separated by the substrate to eventually form a flexible circuit structure.

Reduced Stress And Zero Stress Interposers For Integrated-Circuit Chips, Multichip Substrates, And The Like

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US Patent:
6444921, Sep 3, 2002
Filed:
Feb 3, 2000
Appl. No.:
09/497542
Inventors:
Wen-chou Vincent Wang - Cupertino CA
Michael G. Lee - San Jose CA
Solomon Beilin - San Carlos CA
Assignee:
Fujitsu Limited
International Classification:
H05K 116
US Classification:
174260, 174254, 439 91
Abstract:
Disclosed is an interposer for electrically coupling two electrical components having different coefficients of thermal expansion (CTEs). The interposer has two substrates which have different CTE values, with each substrate having a first surface and a second surface. The interposer has electrical connectors located on the first surfaces of the two substrates, the connectors for making electrical connections to the two corresponding electrical components. A flexible-circuit layer is disposed between the two substrates and interconnects the connectors on the first substrate to the connectors on the second substrate. The two substrates are folded such that their second surfaces confront one another, where they may be attached to one another. General methods of making interposers for electrically coupling two electrical components are disclosed. A first substrate and a sacrificial substrate are encapsulated in an encapsulant material to form a composite substrate, with a second substrate being formed from the cured encapsulate material.

Isolated Flip Chip Of Bga To Minimize Interconnect Stress Due To Thermal Mismatch

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US Patent:
6509529, Jan 21, 2003
Filed:
Sep 20, 2001
Appl. No.:
09/960164
Inventors:
Sundar Kamath - San Jose CA
David Chazan - Palo Alto CA
Jan I. Strandberg - Cupertino CA
Solomon I. Beilin - San Carlos CA
Assignee:
Kulicke Soffa Holdings, Inc. - Willow Grove PA
International Classification:
H05K 103
US Classification:
174255, 174260, 361707, 361711
Abstract:
A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Methods For Detaching A Layer From A Substrate

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US Patent:
6544430, Apr 8, 2003
Filed:
May 31, 2001
Appl. No.:
09/872795
Inventors:
Mark Thomas McCormack - Livermore CA
James Roman - Sunnyvale CA
Lei Zhang - San Jose CA
Solomon I. Beilin - San Carlos CA
Assignee:
Fujitsu Limited
International Classification:
C03C 2568
US Classification:
216 67, 216 40, 216 58, 438697, 438706, 438976, 156246, 156247, 156248, 1562722, 1562726, 1562733, 1562739, 29846, 29849, 427569, 427576, 427579
Abstract:
Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure. Plasma may be used to treat a surface of the release layer or the dielectric film to produce a plasma-treated surface to lower the peel strength of any film or layer bound to the plasma-treated surface.

Methods For Fabricating Flexible Circuit Structures

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US Patent:
6572780, Jun 3, 2003
Filed:
May 31, 2001
Appl. No.:
09/872629
Inventors:
Mark Thomas McCormack - Livermore CA
James Roman - Sunnyvale CA
Lei Zhang - San Jose CA
Solomon I. Beilin - San Carlos CA
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
H01B 1300
US Classification:
216 13, 216 20, 156155, 156246, 156247, 156248
Abstract:
Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure.

Conductive Composition

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US Patent:
6579474, Jun 17, 2003
Filed:
Feb 12, 2001
Appl. No.:
09/782384
Inventors:
Mark Thomas McCormack - San Jose CA
Hunt Hang Jiang - San Jose CA
Solomon I. Beilin - San Carlos CA
Albert Wong Chan - Cupertino CA
Yasuhito Takahashi - San Jose CA
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
H01B 104
US Classification:
252512, 252513, 252514, 2525181, 252500, 148 24, 148 25, 156277
Abstract:
A conductive composition, and articles and methods using the conductive composition are disclosed.

Opto-Electronic Substrates With Electrical And Optical Interconnections And Methods For Making

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US Patent:
6611635, Aug 26, 2003
Filed:
Apr 20, 1999
Appl. No.:
09/295628
Inventors:
Tetsuzo Yoshimura - Sunnyvale CA
Masaaki Inao - San Jose CA
Michael G. Lee - San Jose CA
William Chou - Cupertino CA
Solomon I. Beilin - San Carlos CA
Wen-chou Vincent Wang - Cupertino CA
James J. Roman - Sunnyvale CA
Thomas J. Massingill - Scotts Valley CA
Assignee:
Fujitsu Limited
International Classification:
G02B 612
US Classification:
385 14, 385 49, 385 88
Abstract:
Disclosed is device and/or material integration into thin opto-electronic layers, which increase room for chip-mounting, and reduce the total system cost by eliminating the difficulty of optical alignment between opto-electronic devices and optical waveguides. Opto-electronic devices are integrated with optical waveguides in ultra thin polymer layers on the order of 1 m to 250 m in thickness.
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Solomon I Beilin from San Carlos, CA, age ~89 Get Report