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Reza R Arghavani

from Albuquerque, NM
Age ~63
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Also known as:
Mohammad R Arghavani, Reiza Arghavani
Related to:
Sarah E Arghavani, 25Miriam M ArghavaniWilliam F Stoner, 85Daniel Mehrdad Arghavani, 27Barbara T Stoner, 80Mohammad R Arghavani, 63Dorothy L StonerTamera J Arghavani, 58Veronica L Stoner, 59Chantal J Stoner, 48
Connected to:
David Arghavani, 57Carmen E Argibay, 81Jesus Argil, 39Karla J Argil, 33Ann E Argila, 55Julia M Argila, 70Brian Argilagos, 42Lisa B Argilagos, 60Theodore D Argilan, 74Ronald L Argillander, 79

Reza Arghavani Phones & Addresses

  • Albuquerque, NM
  • College Station, TX
  • Aloha, OR
  • 192 Twin Pines Dr, Scotts Valley, CA 95066 (831) 440-9923
  • Santa Cruz, CA
  • Santa Clara, CA

Work

Company: Lam research corporation 2010 Position: Managing director

Education

Degree: B.S., M.S., Ph.D. School / High School: University of California, Los Angeles Specialities: Solid State Physics

Skills

Semiconductor Manufacturing • Development • Semiconductors • Research • Engineering Management • Process Development • Integration • Semiconductor • Characterization • San

Emails

r***[email protected]

Industries

Semiconductors

Resumes

Resumes

Reza Arghavani Photo 1

Sandia National Laboratories + Adjunct Professor-Tohoku University, Japan

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Location:
192 Twin Pines Dr, Scotts Valley, CA 95066
Industry:
Semiconductors
Work:
Lam Research Corporation since 2010
Managing Director
Universal Phase, Inc. 2009 - 2010
CTO and Co-Founder
Applied Materials 2002 - 2009
Fellow
Intel 1991 - 2002
Logic Technology Development
Education:
University of California, Los Angeles
B.S., M.S., Ph.D., Solid State Physics
Skills:
Semiconductor Manufacturing
Development
Semiconductors
Research
Engineering Management
Process Development
Integration
Semiconductor
Characterization
San

Publications

Us Patents

N2O Nitrided-Oxide Trench Sidewalls To Prevent Boron Outdiffusion And Decrease Stress

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US Patent:
6566727, May 20, 2003
Filed:
Nov 3, 1999
Appl. No.:
09/433541
Inventors:
Reza Arghavani - Aloha OR
Robert S. Chau - Beaverton OR
Simon Yang - Portland OR
John Graham - Fort Collins CO
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2500
US Classification:
257506
Abstract:
A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.

Integrated Circuit With Multiple Gate Dielectric Structures

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US Patent:
6597046, Jul 22, 2003
Filed:
Aug 20, 1999
Appl. No.:
09/378053
Inventors:
Robert S. Chau - Beaverton OR
Reza Arghavani - Aloha OR
Bruce Beattie - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2976
US Classification:
257411, 257406, 257410, 438216, 438261, 438287, 438591
Abstract:
An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface. In one embodiment the gate dielectric is an oxynitride formed by an N plasma; and the oxynitride has top surface nitrogen concentration that is higher than a bottom surface nitrogen concentration. In a further aspect of the present invention, an integrated circuit includes a plurality of IGFETs, wherein various ones of the plurality of IGFETs have different gate dielectric thicknesses and compositions. A method of forming IGFETs with different gate dielectric thicknesses and compositions, on a single integrated circuit, includes forming a first oxynitride layer, forming a masking layer, removing a portion of the first oxynitride layer, forming an oxide layer where the oxynitride was removed, and forming a plurality of gate electrodes, a first portion of the gate electrodes overlying the first oxynitride layer.

Plasma Nitridation For Reduced Leakage Gate Dielectric Layers

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US Patent:
6610615, Aug 26, 2003
Filed:
Nov 15, 2000
Appl. No.:
09/714001
Inventors:
Robert McFadden - Beaverton OR
Jack Kavalieros - Portland OR
Reza Arghavani - Aloha OR
Doug Barlage - Portland OR
Robert Chau - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2131
US Classification:
438776, 438197, 438777
Abstract:
A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be used in combination with nitrogen to produce a lower power plasma resulting in a steeper concentration curve for nitrogen in the silicon oxide film.

Method For Making A Semiconductor Device Having A High-K Gate Dielectric

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US Patent:
6617209, Sep 9, 2003
Filed:
Feb 22, 2002
Appl. No.:
10/082530
Inventors:
Robert Chau - Beaverton OR
Reza Arghavani - Aloha OR
Mark Doczy - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 218242
US Classification:
438240, 438554, 438 3
Abstract:
A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.

Method For Making A Semiconductor Device Having A High-K Gate Dielectric

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US Patent:
6617210, Sep 9, 2003
Filed:
May 31, 2002
Appl. No.:
10/159520
Inventors:
Robert Chau - Beaverton OR
Reza Arghavani - Aloha OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 218242
US Classification:
438240, 438287, 438591, 438624, 438763, 438775, 438791
Abstract:
A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. An insulating layer, which is compatible with the dielectric layer and a gate electrode to be formed on the insulating layer, is formed on the dielectric layer, and a gate electrode is then formed on the insulating layer.

Interfacial Layer For Gate Electrode And High-K Dielectric Layer And Methods Of Fabrication

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US Patent:
6620713, Sep 16, 2003
Filed:
Jan 2, 2002
Appl. No.:
10/038410
Inventors:
Reza Arghavani - Aloha OR
Robert Chau - Beaverton OR
Mark Doczy - Beaverton OR
Brian Roberds - Escondido CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 213205
US Classification:
438585
Abstract:
Method of fabricating a semiconductor device. The semiconductor device comprises a substrate, a high-k gate dielectric layer formed on the substrate, and a hydrogen-free gate electrode deposited on the high-k gate dielectric layer wherein the hydrogen-free gate electrode is conductive. The method comprises depositing the high-k gate dielectric layer on the substrate, sputtering the gate electrode on the gate dielectric layer and treating the gate electrode such that the gate electrode is conductive.

Thin Dielectric Layers And Non-Thermal Formation Thereof

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US Patent:
6667232, Dec 23, 2003
Filed:
Dec 8, 1998
Appl. No.:
09/208268
Inventors:
Steven J. Keating - Beaverton OR
Robert S. Chau - Aloha OR
Reza Arghavani - Aloha OR
Jack T. Kavalieros - Portland OR
Douglas W. Barlage - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 214763
US Classification:
438632, 438637, 438762, 438769, 438770, 438954, 257313, 257411, 257639
Abstract:
A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80Â C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24Â C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.

Plasma Nitridation For Reduced Leakage Gate Dielectric Layers

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US Patent:
6667251, Dec 23, 2003
Filed:
Jun 11, 2003
Appl. No.:
10/460498
Inventors:
Robert McFadden - Beaverton OR
Jack Kavalieros - Portland OR
Reza Arghavani - Aloha OR
Doug Barlage - Portland OR
Robert Chau - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2131
US Classification:
438795, 438775, 257649
Abstract:
A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be used in combination with nitrogen to produce a lower power plasma resulting in a steeper concentration curve for nitrogen in the silicon oxide film.
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Reza R Arghavani from Albuquerque, NM, age ~63 Get Report