Search

Rex E Lowther

from Palm Bay, FL
Age ~71

Rex Lowther Phones & Addresses

  • 955 Peachland Ave NE, Palm Bay, FL 32907 (321) 951-0248 (321) 676-0354
  • Melbourne, FL
  • 955 Peachland Ave NE, Palm Bay, FL 32907 (321) 377-9420

Work

Position: Clerical/White Collar

Education

Degree: High school graduate or higher

Emails

Resumes

Resumes

Rex Lowther Photo 1

Senior Scientist At Silicon Space Technology

View page
Position:
Senior Scientist at Silicon Space Technology
Location:
Melbourne, Florida Area
Industry:
Electrical/Electronic Manufacturing
Work:
Silicon Space Technology
Senior Scientist

Harris Semiconductor 1981 - 1995
Sr. Scientist
Rex Lowther Photo 2

Rex Lowther

View page
Location:
United States
Work:
Silicon Space Technology 2005 - 2013
Senior Scientist
Rex Lowther Photo 3

Rex Lowther

View page

Publications

Us Patents

Symmetric Inducting Device For An Integrated Circuit Having A Ground Shield

View page
US Patent:
6635949, Oct 21, 2003
Filed:
Jan 4, 2002
Appl. No.:
10/039200
Inventors:
Rex Everett Lowther - Palm Bay FL
William R. Young - Palm Bay FL
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
H01L 2900
US Classification:
257531, 257277, 257351, 257495, 257528, 336223
Abstract:
The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate has a working surface. The main metal layer has at least one pair of current path regions. Each of the current path region pairs is formed in generally a regular polygonal shape that is generally symmetric about a plane of symmetry that is perpendicular to the working surface of the substrate. The shield is patterned into segments that are generally symmetric about the plane of symmetry. Medial portions of at least some segments of the shield are formed generally perpendicular to the plane of symmetry as the medial portions cross the plane of symmetry.

Radiation Immunity Of Integrated Circuits Using Backside Die Contact And Electrically Conductive Layers

View page
US Patent:
20080142899, Jun 19, 2008
Filed:
Aug 4, 2007
Appl. No.:
11/833989
Inventors:
Wesley H. Morris - Austin TX,
Jon Gwin - San Antonio TX,
Rex Lowther - Palm Bay FL,
Assignee:
SILICON SPACE TECHNOLOGY CORPORATION - Austin TX
International Classification:
H01L 29/36
H01L 21/223
US Classification:
257371, 438526, 257369, 257E29109, 257E21143
Abstract:
Radiation hardened integrated circuit devices may be fabricated using conventional designs and process, but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. An exemplary BGR structure includes a high-dose buried guard ring (HBGR) layer which is contacted to ground through the backside of the wafer or circuit die, thus forming a Backside BGR (BBGR) structure. In certain embodiments, the starting wafer may be highly doped to reduce the resistance from the HBGR to the back of the wafer, which is then further contacted to ground through the package. The performance of such devices may be further improved by using an electrically conductive adhesive to attach the die and to electrically connect the silicon substrate region to the package's conductive header, substrate, or die attach pad, which in turn is typically connected to one or more package pins/balls.

Electric Field Fingerprint Sensor Having Enhanced Features And Related Methods

View page
US Patent:
59405260, Aug 17, 1999
Filed:
May 16, 1997
Appl. No.:
8/858144
Inventors:
Dale R. Setlak - Melbourne FL
Nicolaas W. Van Vonno - Melbourne FL
Rex Lowther - Palm Bay FL
Dave Gebauer - West Melbourne FL
Assignee:
Harris Corporation - Palm Bay FL
International Classification:
G06K 900
US Classification:
382124
Abstract:
A fingerprint sensor includes a plurality of semiconductor devices adjacent a substrate and defining active circuit portions, and having only three metal layers. More particularly, the sensor may include a first metal layer interconnecting predetermined ones of the plurality of semiconductor devices; a second metal layer defining a ground plane; and a third metal layer comprising an array of electric field sensing electrodes connected to active circuit portions for generating an output related to a sensed fingerprint. The fingerprint sensor may also include a package surrounding the substrate and having an opening aligned with the sensing electrodes. In addition, a first external electrode may be carried by the package for contact by a finger. The sensor may thus also include an excitation drive circuit connected between the ground plane and the first external electrode for generating electric fields between the electric field sensing electrodes and adjacent finger portions. A power control circuit is for controlling operation of active circuit portions based upon sensing finger contact with the first external electrode so that the active circuit portions are powered upon sensing finger contact with the first external electrode and otherwise grounded.

Structure And Technique For Tailoring Effective Resistivity Of A Sipos Layer By Patterning And Control Of Dopant Introduction

View page
US Patent:
56379080, Jun 10, 1997
Filed:
Sep 28, 1994
Appl. No.:
8/314489
Inventors:
Rex E. Lowther - Palm Bay FL
James D. Beason - Melbourne FL
Assignee:
Harris Corporation - Melbourne FL
International Classification:
H01L 2934
H01L 27098
H01L 2702
H01L 2940
US Classification:
257489
Abstract:
An increase in breakdown voltage of a semiconductor device upon which a layer of high resistance material, such as SIPOS, has been formed is achieved by controllably modifying the physical composition of the high resistance layer, for example by patterning a plurality of generally wedge-shaped apertures into the layer, so that the electric field in the underlying substrate is made more uniform across the surface of the device. This increase in uniformity in the radial direction effectively spreads out or reduces the field away from its normal peak region near the corner of the drain/substrate PN junction. In most versions of this device, an additional advantage--decreased leakage current--is realized.

Electrostatic Discharge Locating Apparatus And Method

View page
US Patent:
60643404, May 16, 2000
Filed:
Jul 2, 1998
Appl. No.:
9/108963
Inventors:
Gregg D. Croft - Palm Bay FL
Joseph C. Bernier - Palm Bay FL
Rex Lowther - Palm Bay FL
Assignee:
Intersil Corporation - Palm Bay FL
International Classification:
G01S 302
G01S 3102
US Classification:
342460
Abstract:
An electrostatic discharge locating system may include a plurality of receivers and a central unit. Each receiver may include an antenna. The receivers may receive radio wave signals emanating from an electrostatic discharge event and transmit the signals to the central unit for processing. The central unit may determine the location of an electrostatic discharge event from the relative time of signal reception or the signal amplitudes along with predetermined locations of the receivers.

Integrated Circuit With An Improved Inductor Structure And Method Of Fabrication

View page
US Patent:
57172439, Feb 10, 1998
Filed:
Apr 24, 1996
Appl. No.:
8/637132
Inventors:
Rex Everett Lowther - Palm Bay FL
Assignee:
Harris Corporation - Palm Bay FL
International Classification:
H01L 2900
US Classification:
257531
Abstract:
An integrated circuit with an inductor structure includes a semiconductor device substrate. Over the semiconductor device substrate is a dielectric layer, and over the dielectric layer is a metal spiral inductor. The metal spiral is formed by a continuous metal strip. The continuous metal strip has at one end a center and then increases in a radial direction to its other end. The metal spiral carries current between its two ends and generates radial and circumferential parasitic currents in the substrate. In the substrate are a plurality of separated radial doped strips about a central axis. Each of these radial doped strips define a region of relative low resistivity to reduce the resistance to the radial current flow in the device substrate. These strips are separated by regions having relatively high resistivity to substantially maintain the resistance to the circumferential current flow in the substrate. The integrated circuit may also have a metal line extending over the dielectric layer in an incomplete ring around the outer circumference of the metal spiral.

Semi-Insulating Wafer

View page
US Patent:
57731519, Jun 30, 1998
Filed:
Jun 30, 1995
Appl. No.:
8/497404
Inventors:
Patrick A. Begley - West Melbourne FL
Anthony Rivoli - Palm Bay FL
Gyorgy Bajor - Melbourne FL
Rex E. Lowther - Palm Bay FL
Assignee:
Harris Corporation - Melbourne FL
International Classification:
B32B 904
US Classification:
428446
Abstract:
A bonded wafer 10 has a silicon device layer 20 bonded to a layer of semi-insulating material 14, preferably a mobility degraded silicon such as polycrystaline silicon. Layer 14 is thick enough and substrate 16 is conductive enough to reduce resistive losses when devices in layer 20 are operated at frequencies above 0. 1 Ghz. Substrate 16 is conductive enough and semi-insulating material 14 is resistive enough to prevent cross-talk among devices in layer 20.

Fast Charging Mos Capacitor Structure For High Magnitude Voltage Of Either Positive Or Negative Polarity

View page
US Patent:
53410092, Aug 23, 1994
Filed:
Jul 9, 1993
Appl. No.:
8/090978
Inventors:
Dennis C. Young - Melbourne FL
Rex E. Lowther - Palm Bay FL
Assignee:
Harris Corporation - Melbourne FL
International Classification:
H01L 2702
H01G 1005
US Classification:
257296
Abstract:
Depletion layer depth and semiconductor real estate occupation area shortcomings of conventional MOS capacitor architectures that are formed on lightly doped semiconductor material are obviated by augmenting the MOS capacitor structure with a pair of opposite conductivity type, high impurity concentration regions, both of which are directly contiguous with the lightly doped lower plate layer that underlies the capacitor's dielectric layer, and connecting both of these auxiliary heavily doped regions to a common capacitor electrode terminal for the lower plate of the capacitor. If a high negative charge is applied to the upper plate overlying the thin dielectric layer, holes are readily supplied by the auxiliary P+ region. Conversely, if a high positive charge be applied to the upper plate, electrons are readily supplied by the auxiliary N+ region. By connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage.
Rex E Lowther from Palm Bay, FL, age ~71 Get Report