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Judd E Heape

from San Jose, CA
Age ~52
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Also known as:
Judd Heape, Judd Catherine Heape, Judd Cathy Heape, England Heape Judd
Phone and address:
1539 Arata Ct, San Jose, CA 95125
(408) 293-5833
Related to:
Gene G Heape, 97Catherine A Blum, 57Kaniah HillCarolyn Blum EstIrene E Heape, 93Austin S Heape, 39Irene E HeapeDavid C Heape, 41
Connected to:
Jason A Heape, 51Melissa J Heape, 41Towanda D Heape, 56Victoria G Heape, 77Matthew T Heapes, 41Carrie L Heaphy, 46Franklin J Heaphy, 71Jason Heaphy, 43Lois B Heaphy, 61Neil E Heaphy, 65

Judd Heape Phones & Addresses

  • 1539 Arata Ct, San Jose, CA 95125 (408) 293-5833
  • 2746 Kring Dr, San Jose, CA 95125 (408) 265-5833
  • Carmel, CA
  • Monterey, CA
  • 16804 Davenport Rd, Dallas, TX 75248 (972) 380-5833
  • 18732 Mapletree Ln, Dallas, TX 75252 (972) 380-5833
  • Colton, TX
  • 1539 Arata Ct, San Jose, CA 95125

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Public records

Vehicle Records

Judd Heape

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Address:
1539 Arata Ct, San Jose, CA 95125
Phone:
(408) 490-1908
VIN:
JHLRE38777C081635
Make:
HONDA
Model:
CR-V
Year:
2007

Resumes

Resumes

Judd Heape Photo 1

Senior Director, Product Management, Camera, Computer Vision And Video

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Location:
1539 Arata Ct, San Jose, CA 95125
Industry:
Semiconductors
Work:
Apical Limited - Loughborough, U.K. since Sep 2011
Vice President of Engineering
Altera Jan 2011 - Sep 2011
Sr. Product Marketing Manager, Low Cost Products
Altera Apr 2009 - Jan 2011
Sr. Strategic Marketing Manager
Altera Jul 2008 - Apr 2009
Sr. Technical Marketing Manager
QuickLogic Corp. Jul 2000 - Jun 2008
Principal Architect & Sr. Director, Systems Engineering
Education:
Georgia Institute of Technology 1988 - 1992
BE, Electrical Engineering Trinity Christian Academy 1976 - 1988
Skills:
Fpga
Embedded Systems
Semiconductors
Digital Signal Processors
Soc
Asic
Ic
Hardware Architecture
Semiconductor Industry
Pcb Design
Eda
Processors
Product Marketing
Debugging
Verilog
Technical Marketing
Electronics
Testing
Smartphones
Engineering Management
Analog
Rtl Design
System Architecture
Hardware
System Design
Interests:
Kids
Cooking
Exercise
Gardening
Traveling
Electronics
Home Improvement
Diet
Donor
Reading
Fitness
Gourmet Cooking
Sports
Automobiles
Animal Welfare
Travel
Home Decoration
Languages:
English
Japanese
Judd Heape Photo 2

Judd Heape

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Publications

Us Patents

System Signalling Schemes For Processor Memory Module

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US Patent:
6584588, Jun 24, 2003
Filed:
Oct 30, 2000
Appl. No.:
09/698089
Inventors:
Basavaraj I. Pawate - Ibaraki, JP
Matthew A. Woolsey - Princeton TX
Douglas L. Mahlum - Allen TX
Fred J. Reuter - Plano TX
Yoshihide Iwata - Ibaraki-ken, JP
Judd E. Heape - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 2900
US Classification:
714719
Abstract:
A computer system includes a main processing unit ( ) coupled to a DSP/memory module ( ). The DSP/memory module ( ) includes semiconductor memory ( ) and digital signal processor circuitry ( ) including one or more digital signal processors ( ). The DSP/memory module ( ) may be placed in standard main memory sockets, such as a SIMM or DIMM sockets, and used as conventional main memory. The memory module can also be used in a smart mode, wherein the digital signal processor ( ) performs operations on data for retrieval by the main processing unit ( ).

Automatic Detection And Correction Of Relatively Rearranged And/Or Inverted Data And Address Signals To Shared Memory

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US Patent:
6701418, Mar 2, 2004
Filed:
Dec 3, 2001
Appl. No.:
09/998331
Inventors:
Christopher J. Poletto - Derwood MD
Judd E. Heape - Dallas TX
Steven Trautmann - Tsukuba, JP
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1300
US Classification:
711147, 711202, 711211, 710316, 712300
Abstract:
A set of related methods for detecting the existence and exact nature of any rearrangements and/or inversions of address lines and/or data lines to a memory device, relative to a second set of address lines and/or data lines to the same memory, are disclosed. Moreover, a set of related methods for correcting these relative rearrangements and/or inversions are disclosed. These methods allow meaningful access to memory shared by two or more devices using different address and data paths in the case where the relative nature of the address and data paths is unknown a priori. These methods of detecting and correcting such mismatches in separate address and data lines to shared memory may be implemented either in hardware or software or a combination of both.

Using A Processor Enhanced Memory Module To Accelerate Hardcopy Image Processing Within Existing Printer Controller

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US Patent:
7034955, Apr 25, 2006
Filed:
Dec 3, 2001
Appl. No.:
09/998828
Inventors:
James Glenn Bearss - Boise ID, US
Judd E. Heape - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 15/00
G06F 13/00
US Classification:
358 116, 358 115, 358 113, 358 114, 358 117, 358 118, 358302, 3482072, 3482071, 34820711
Abstract:
The processor enhanced memory module PEMM can be incorporated into the hardcopy image processing pipeline of existing printer controllers by using the smart memory model. Here the data generated from RISC based PDL interpretation or pre-rasterized data can be processed in an accelerated fashion into page bit maps, color space converted, and compressed by the PEMM. Since the DSP on the PEMM is programmable, the resolution, color space, and type of compression along with other printer specific processing can have formats other than those determined by the fixed functionality of the ASIC devices present in the pipeline.

System Signaling Schemes For Processor And Memory Module

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US Patent:
61857041, Feb 6, 2001
Filed:
Apr 9, 1998
Appl. No.:
9/058000
Inventors:
Basavaraj I. Pawate - Ibaraki, JP
Matthew A. Woolsey - Princeton TX
Douglas L. Mahlum - Allen TX
Fred J. Reuter - Plano TX
Yoshihide Iwata - Ibaraki-ken, JP
Judd E. Heape - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 2900
US Classification:
714719
Abstract:
A computer system includes a main processing unit (12) coupled to a DSP/memory module (40). The DSP/memory module (40) includes semiconductor memory (42) and digital signal processor circuitry (44) including one or more digital signal processors (56). The DSP/memory module (40) may be placed in standard main memory sockets, such as a SIMM or DIMM sockets, and used as conventional main memory. The memory module can also be used in a smart mode, wherein the digital signal processor (56) performs operations on data for retrieval by the main processing unit (12).

Method Of Modeling Player Position And Movement In A Virtual Reality System

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US Patent:
60549912, Apr 25, 2000
Filed:
Jul 29, 1994
Appl. No.:
8/282413
Inventors:
Christopher Adam Crane - Washington MO
Tom J. Bannon - Dallas TX
Daniel Martin Donahue - Dallas TX
Donald Wayne Adkins - Oak Leaf TX
Judd England Heape - Dallas TX
Andrew Kendall Smith - Boston MA
Thomas M. Siep - Garland TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06T 1500
US Classification:
345420
Abstract:
In a virtual reality system (20) an operator perceives being in a virtual reality world (74) of virtual reality images (62). The system (20) models the relative position and movement of objects (208 and 210) in a virtual reality world (74) by representing graphically a first (208) and second (210) object in a virtual reality world (74) on a graphical display (60 and 68). The representation selective obscures the first (208) and second (210) objects according to the relative position of the objects (208 and 210) to a predetermined observation point in the virtual reality world (74). The system (20) then determines a first partitioning plane (204) between the first (208) and second (210) objects. Then, the system (20) method determines a second partition plane (206) between the first (208) and second (210) object in response to either of said first (208) or second (210) objects moving across the first partitioning plane (204). Then, the system (20) graphically represent on the graphical display (60 and 68) the first (208) and second (210) objects within the virtual reality world (74) by selectively obscuring the first (208) and second (210) objects according to their relative position to the predetermined observation point.
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Judd E Heape from San Jose, CA, age ~52 Get Report