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Jerome Imonigie Phones & Addresses

  • Boise, ID
  • 1306 5Th St, Meridian, ID 83642 (208) 855-2181
  • 1433 5Th St, Meridian, ID 83642
  • 122 Jessup Rd, Henderson, NV 89014
  • Alpharetta, GA
  • Atlanta, GA
  • Laramie, WY
  • 12474 W Abram Dr, Boise, ID 83713

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

Publications

Us Patents

Methods Of Forming Memory Cells, And Methods Of Patterning Chalcogenide-Containing Stacks

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US Patent:
20120015475, Jan 19, 2012
Filed:
Jul 14, 2010
Appl. No.:
12/836476
Inventors:
Jun Liu - Boise ID, US
Jerome Imonigie - Boise ID, US
International Classification:
H01L 21/06
H01L 21/306
US Classification:
438102, 438706, 257E21068, 257E21215
Abstract:
Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of HOand HNOto remove damaged chalcogenide from the sidewalls of the memory cell structures.

Methods Of Selectively Forming Metal-Doped Chalcogenide Materials, Methods Of Selectively Doping Chalcogenide Materials, And Methods Of Forming Semiconductor Device Structures Including Same

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US Patent:
20120276725, Nov 1, 2012
Filed:
Apr 26, 2011
Appl. No.:
13/094024
Inventors:
Jerome A. Imonigie - Boise ID, US
Prashant Raghu - Boise ID, US
Theodore M. Taylor - Boise ID, US
Scott E. Sills - Boise ID, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
H01L 21/228
H01B 1/02
US Classification:
438542, 252512, 252514, 252513, 257E21153
Abstract:
Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material. A method of doping a chalcogenide material of a memory cell with at least one transition metal without using an etch or chemical mechanical planarization process to remove the transition metal from an insulative material of the memory cell is also disclosed, wherein the chalcogenide material is not silver selenide.

Methods Of Forming Memory Cells, And Methods Of Patterning Chalcogenide-Containing Stacks

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US Patent:
20130149834, Jun 13, 2013
Filed:
Feb 7, 2013
Appl. No.:
13/761609
Inventors:
MICRON TECHNOLOGY INC. - Boise ID, US
Jerome Imonigie - Boise ID, US
Assignee:
MICRON TECHNOLOGY, INC. - Boise ID
International Classification:
H01L 45/00
US Classification:
438381, 438706
Abstract:
Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of HOand HNOto remove damaged chalcogenide from the sidewalls of the memory cell structures.

Recessed Gate Memory Apparatuses And Methods

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US Patent:
20130334594, Dec 19, 2013
Filed:
Jun 15, 2012
Appl. No.:
13/524803
Inventors:
Jerome A. Imonigie - Boise ID, US
Patrick M. Flynn - Boise ID, US
Sandra L. Tagg - Boise ID, US
Prashant Raghu - Boise ID, US
International Classification:
H01L 29/792
H01L 21/28
H01L 21/306
US Classification:
257326, 438706, 438589, 257E29309, 257E21215, 257E2119
Abstract:
Some embodiments include a memory device and a method of forming the memory device. One such memory device includes a string of stacked memory cells. Each of the memory cells in the string includes a charge storage structure and a recessed control gate. The recessed control gate has a substantially smooth surface separated from the charge storage structure by dielectric material. One such method includes etching heavily boron doped polysilicon selective to oxide to form a recessed control gate having a surface with nubs. A smoothing solution is applied to the surface of the recessed control gate to smoothen the nubs. Additional apparatuses and methods are described.
Jerome A Imonigie from Boise, ID, age ~60 Get Report