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Helmut Tews Phones & Addresses

  • 26 Millbank Rd, Poughkeepsie, NY 12603 (845) 462-2982
  • 4 Cabin Way, Poughkeepsie, NY 12603
  • Cheyenne, WY

Publications

Us Patents

Integrated Circuit Vertical Trench Device And Method Of Forming Thereof

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US Patent:
6335247, Jan 1, 2002
Filed:
Jun 19, 2000
Appl. No.:
09/597389
Inventors:
Helmut Horst Tews - Poughkeepsie NY
Alexander Michaelis - Dormagen, DE
Stephan Kudelka - Fishkill NY
Uwe Schroeder - Fishkill NY
Brian S. Lee - New York NY
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 21336
US Classification:
438270, 438268, 438733
Abstract:
A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e. g. , isolation collar ) is protected by a mask (e. g. , polysilicon ), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall ( ) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e. g. silicon dioxide ) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

Process For Fabricating A Uniform Gate Oxide Of A Vertical Transistor

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US Patent:
6348388, Feb 19, 2002
Filed:
Sep 20, 2000
Appl. No.:
09/668638
Inventors:
Johnathan E. Faltermeier - Lagrange NY
Ulrike Gruening - Wappingers Falls NY
Suryanarayan G. Hegde - New York NY
Rajarao Jammy - Wappingers Falls NY
Brian S. Lee - New York NY
Helmut H. Tews - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies North America Corp. - San Jose CA
International Classification:
H01L 21336
US Classification:
438303, 438931, 438238
Abstract:
A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a crystal plane and a crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the crystal plane of the trench side wall, but not into the crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Orientation Independent Oxidation Of Silicon

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US Patent:
6358867, Mar 19, 2002
Filed:
Jun 16, 2000
Appl. No.:
09/596097
Inventors:
Helmut Horst Tews - Poughkeepsie NY
Jonathan E. Faltermeir - LaGrange NY
Rajeev Malik - Pleasantville NY
Carol Heenan - LaGrangeville NY
Oleg Gluschenkov - Poughkeepsie NY
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2131
US Classification:
438771, 438770, 438787, 438788, 438973, 438198
Abstract:
A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate where silicon surfaces have at least two different crystallographic orientations of the silicon crystal. Atomic oxygen (O) is formed for oxidizing the surfaces. An oxide is formed on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.

Reduction Of Orientation Dependent Oxidation For Vertical Sidewalls Of Semiconductor Substrates

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US Patent:
6362040, Mar 26, 2002
Filed:
Feb 9, 2000
Appl. No.:
09/501502
Inventors:
Helmut Horst Tews - Poughkeepsie NY
Brian S. Lee - New York NY
Ulrike Gruening - Munich, DE
Raj Jammy - Wappingers Falls NY
John Faltermeier - LaGrange NY
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
H01L 218242
US Classification:
438246, 438243, 438244, 438245, 438247, 438248, 438249, 438386, 438387, 438388, 438389, 438390, 438391, 438392
Abstract:
A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer.

Control Of Oxide Thickness In Vertical Transistor Structures

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US Patent:
6372567, Apr 16, 2002
Filed:
Apr 20, 2000
Appl. No.:
09/553708
Inventors:
Helmut Horst Tews - Poughkeepsie NY
Brian S. Lee - New York NY
Ulrike Gruening - Munich, DE
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 218238
US Classification:
438212, 438149, 438210, 438244, 156643
Abstract:
Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.

Light Source For Generating A Visible Light

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US Patent:
6396081, May 28, 2002
Filed:
Apr 2, 2001
Appl. No.:
09/720695
Inventors:
Helmut Tews - Poughkeepsie NY
Robert Averbeck - Munich, DE
Henning Riechert - Ottobrun, DE
Assignee:
Osram Opto Semiconductor GmbH Co. OHG - Regensburg
International Classification:
H01L 2715
US Classification:
257 79, 257 80, 438 22
Abstract:
Light source ( ) for generating visible light ( ), comprising at least one diode ( ) on a semiconductor basis emitting ultraviolet light ( ) and at least one luminophor ( ) into which the emitted ultraviolet light ( ) beams and which generates the visible light from the emitted ultraviolet light ( ). Application: Generation of white light offering especially high color fidelity.

Method Of Forming A Vertically Oriented Device In An Integrated Circuit

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US Patent:
6426253, Jul 30, 2002
Filed:
May 23, 2000
Appl. No.:
09/576465
Inventors:
Helmut Horst Tews - Poughkeepsie NY
Alexander Michaelis - Dormagen, DE
Brian S. Lee - New York NY
Uwe Schroeder - Fishkill NY
Stephan Kudelka - Fishkill NY
Assignee:
Infineon Technologies A G - Munich
International Classification:
H01L 218242
US Classification:
438243, 438386
Abstract:
A system and method of forming an electrical connection ( ) to the interior of a deep trench ( ) in an integrated circuit utilizing a low-angle dopant implantation ( ) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate ( ) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material ( ) overlying or in the trench, leaving a self-aligned mask ( ) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

Combined Preanneal/Oxidation Step Using Rapid Thermal Processing

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US Patent:
6436846, Aug 20, 2002
Filed:
Sep 3, 1998
Appl. No.:
09/146870
Inventors:
Helmut Horst Tews - Poughkeepsie NY
Martin Schrems - Langenbrueck, DE
Thomas Gaertner - Ottendorf-Okrilla, DE
Assignee:
Siemens Aktiengesellscharft - Munich
International Classification:
H01L 21469
US Classification:
438770, 438471, 438477, 438787
Abstract:
A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.
Helmut H Tews from Poughkeepsie, NY, age ~73 Get Report