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Douglas A Prinslow

from McKinney, TX
Age ~59

Douglas Prinslow Phones & Addresses

  • 2511 Saint Remy Dr, McKinney, TX 75070 (972) 562-5512
  • Mc Kinney, TX
  • Plano, TX
  • Salt Lake City, UT

Publications

Us Patents

Silicided Undoped Polysilicon For Capacitor Bottom Plate

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US Patent:
6380609, Apr 30, 2002
Filed:
Sep 14, 2000
Appl. No.:
09/661717
Inventors:
Douglas A. Prinslow - McKinney TX
F. Scott Johnson - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2900
US Classification:
257532, 438393, 438396
Abstract:
A capacitor ( ) having a bottom plate ( ) that comprises undoped polysilicon ( ) which has been silicided ( ). An advantage of the invention is providing a capacitor ( ) having reduced parasitic capacitance to the substrate ( ) and reduced sheet resistance of the bottom plate ( ).

Self-Aligned Silicide Process

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US Patent:
6458711, Oct 1, 2002
Filed:
Mar 20, 1998
Appl. No.:
09/045009
Inventors:
Sean C. OBrien - Plano TX
Douglas A. Prinslow - McKinney TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21302
US Classification:
438745, 438753, 438754, 438755
Abstract:
A self-aligned silicide process with a selective etch of unreacted metal (plus any nitride) with respect to silicide plus a two step process of highly selective strip of unreacted metal (plus any nitride) followed by a silicide etch to remove unwanted silicide filament.

Versatile System For Integrated Circuit Containing Shielded Inductor

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US Patent:
6600208, Jul 29, 2003
Filed:
Sep 10, 2001
Appl. No.:
09/953515
Inventors:
Kenneth D. Brennan - Flower Mound TX
Douglas A. Prinslow - McKinney TX
David B. Aldrich - Allen TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2900
US Classification:
257531
Abstract:
A versatile system for reducing electromagnetic interference resulting from an inductor ( ) formed within an integrated circuit is disclosed, including an inductor layer ( ) having conductive elements ( ) about its perimeter, first ( ) and second ( ) isolation layers disposed upon on opposite sides of the inductor layer and having conductive elements ( ) about their perimeters, and first ( ) and second ( ) shield layers surrounding the first and second isolation layers, respectively, and coupled together by the conductive elements ( ) of the isolation and inductor layers.

Silicided Undoped Polysilicon For Capacitor Bottom Plate

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US Patent:
6620700, Sep 16, 2003
Filed:
Mar 20, 2002
Appl. No.:
10/102416
Inventors:
Douglas A. Prinslow - McKinney TX
F. Scott Johnson - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 218242
US Classification:
438393, 438250, 438253, 438396
Abstract:
A capacitor ( ) having a bottom plate ( ) that includes undoped polysilicon ( ) which has been silicided ( ). An advantage of the invention is providing a capacitor ( ) having reduced parasitic capacitance to the substrate ( ) and reduced sheet resistance of the bottom plate ( ).

Low Current Substantially Silicide Fuse For Integrated Circuits

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US Patent:
6642601, Nov 4, 2003
Filed:
Oct 25, 2001
Appl. No.:
10/001591
Inventors:
Andrew Marshall - Dallas TX
Douglas A. Prinslow - McKinney TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2900
US Classification:
257529, 257625, 257755, 257773
Abstract:
A fuse ( ) with a low fusing current includes a first contact element ( ) and a second contact element ( ). A fusing element ( ) is coupled between the first and second contact elements ( ). At least a majority of the fusing element ( ) comprises silicided material.

System For Integrating A Toroidal Inductor In A Semiconductor Device

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US Patent:
7109838, Sep 19, 2006
Filed:
Sep 10, 2001
Appl. No.:
09/953310
Inventors:
Kenneth D. Brennan - Flower Mound TX,
Douglas A. Prinslow - McKinney TX,
David B. Aldrich - Allen TX,
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01F 5/00
US Classification:
336200, 336229
Abstract:
An inductor integrated in a semiconductor device comprises a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a first end of the first lower electrical trace and at a second end with a second end of the second lower electrical trace, a first via intercoupling the first end of the upper electrical trace with the first end of the first lower electrical trace, and a second via intercoupling the second end of the upper electrical trace with the second end of the second lower electrical trace.

Methods And Devices For Determining Logical To Physical Mapping On An Integrated Circuit

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US Patent:
2013032, Dec 12, 2013
Filed:
Jun 7, 2012
Appl. No.:
13/491429
Inventors:
Stanton Petree Ashburn - McKinney TX,
Daniel L. Corum - Richardson TX,
Abha Singh Kasper - Fairview TX,
Harold C. Waite - Rockwall TX,
Eric D. Rullan - Allen TX,
Donald L. Plumton - Dallas TX,
Douglas A. Prinslow - McKinney TX,
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 29/00
H01L 21/02
US Classification:
365200, 438 4, 257E21002
Abstract:
Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.

Sic Sidewall Process

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US Patent:
6262445, Jul 17, 2001
Filed:
Mar 25, 1999
Appl. No.:
9/276047
Inventors:
Leland S. Swanson - McKinney TX
Douglas A. Prinslow - McKinney TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2976
US Classification:
257288
Abstract:
The use of silicon carbide to form sidewall spacers allows the use of a lower temperature deposition step, and provides greater etch selectivity with respect to oxide.
Douglas A Prinslow from McKinney, TX, age ~59 Get Report