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Baolin Yang Phones & Addresses

  • Shoreview, MN
  • Mountain View, CA
  • 1587 Eto Ln, Los Osos, CA 93402
  • 1541 El Tigre Ct, San Luis Obispo, CA 93405 (805) 783-2576
  • 1037 Southwood Dr, San Luis Obispo, CA 93401 (805) 783-2576
  • 1057 Southwood Dr, San Luis Obispo, CA 93401
  • Sn Luis Obisp, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Baolin Yang
Principal
Gemini Design Technology Inc
Business Services
832 Gest Dr, Mountain View, CA 94040

Publications

Us Patents

Method And Device For Multi-Interval Collocation For Efficient High Accuracy Circuit Simulation

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US Patent:
7035782, Apr 25, 2006
Filed:
Jun 1, 2001
Appl. No.:
09/873988
Inventors:
Baolin Yang - Fremont CA,
Joel Phillips - Sunnyvale CA,
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
703 14, 703 2, 716 6
Abstract:
A method and apparatus are provided for solving a set of differential-algebraic equation arising in a circuit simulation is provided. A collocation method is applied to each differential-algebraic equation to discretize the set of differential-algebraic equations. A solution to the set of differential-algebraic equations based on the discretized differential-algebraic equation is then formed.

System And Method For High-Order Accurate Device Model Approximation

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US Patent:
7266479, Sep 4, 2007
Filed:
Jun 18, 2003
Appl. No.:
10/465908
Inventors:
Baolin Yang - Fremont CA,
Bruce W. McGaughy - Fremont CA,
Assignee:
Cadence Designs Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
G06T 17/20
G06F 17/10
US Classification:
703 2, 703 13, 702 16, 345423
Abstract:
An system and method are disclosed for efficiently approximating analytical circuit device models. A preferred embodiment includes a method for obtaining smooth and accurate approximations of analytical device models, comprising the steps of identifying a first set of measurement units; locating two or more sets of units that neighbor one or more of said measurement units; for each set of the two or more sets of neighbor units, obtaining the union of one or more of said sets of neighbor units and the first set of measurement units; calculating the smoothness of the analytical device model within one or more of said unions; and selecting at least one of said unions within which the analytical device model is the smoothest as the new set of measurement units.

Electrical Isomorphism

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US Patent:
7373289, May 13, 2008
Filed:
Nov 19, 2004
Appl. No.:
10/993687
Inventors:
Bruce W. McGaughy - Fremont CA,
Wai Chung William Au - San Jose CA,
Baolin Yang - Fremont CA,
Assignee:
Cadence Design Systems, Inc - San Jose CA
International Classification:
G06F 17/50
US Classification:
703 14
Abstract:
Method and system for determining electrical isomorphism between two electrical networks are disclosed. In one embodiment, the method includes representing the circuit as a hierarchically-arranged set of branches. The hierarchically-arranged set of branches including a first branch that includes a first electrical network and a second branch that includes a second electrical network, where the first and second branches are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. Next, the method determines whether the first and second electrical networks are electrically isomorphic networks. If the first and second electrical networks are determined to be electrically isomorphic networks, the first and second electrical networks are represented with a single electrically isomorphic network. The method further includes simulating the first and second electrical networks using the single electrically isomorphic network.

Simulation Of Electrical Circuits

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US Patent:
7428477, Sep 23, 2008
Filed:
Dec 31, 2002
Appl. No.:
10/335063
Inventors:
Joel R. Phillips - Sunnyvale CA,
Baolin Yang - Fremont CA,
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/10
G06F 17/50
US Classification:
703 2, 703 14, 716 7
Abstract:
A method, computer program product, and apparatus for simulating circuits. The method comprises modeling a circuit with an appropriate system of equations, partitioning a time interval on which the system of equations is defined, producing an interpolating polynomial on the time interval, and applying a two tiered iterative approach to solve the system of equations. The approach begins by decomposing a candidate solution vector into its time domain and frequency domain components. The Fourier transform is applied to the frequency domain components and time domain methods are applied to both the time domain components and the Fourier transformed frequency domain components to generate the solution to the original system of equations. Newton's method can be used in combination with a Krylov iterative subspace solver to perform the two-tiered iteration. The computer program product and the apparatus implement the method of simulating circuits.

Method For Ranking Webpages Via Circuit Simulation

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US Patent:
7483820, Jan 27, 2009
Filed:
Apr 17, 2007
Appl. No.:
11/736259
Inventors:
Baolin Yang - Fremont CA,
Assignee:
Gemini Design Technology, Inc. - Fremont CA
International Classification:
G06F 9/455
US Classification:
703 6, 707 1, 715206, 705 10
Abstract:
In one embodiment, a method for ranking webpages is provided. The method includes generating a web circuit model having a node representing each webpage. The model is simulated to identify the potential at each node. The webpages can then be ranked according to the potentials of the nodes to which the webpages correspond.

Parallel Multi-Rate Circuit Simulation

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US Patent:
7783465, Aug 24, 2010
Filed:
Dec 18, 2006
Appl. No.:
11/612335
Inventors:
Baolin Yang - Fremont CA,
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
703 14
Abstract:
A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, and splitting the Jacobian matrix into two matrices M and N, where M is a matrix suitable for parallel processing and N is a coupling matrix. M and N are then preconditioned to form MJx=(I+MN)x=Mr and the Jacobian matrix J is solved using an iterative solving method.

System And Method For Supporting Multi-Rate Simulation Of A Circuit Having Hierarchical Data Structure

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US Patent:
7269541, Sep 11, 2007
Filed:
Nov 13, 2003
Appl. No.:
10/713753
Inventors:
Bruce W. McGaughy - Fremont CA,
Peter Frey - Campbell CA,
Jun Kong - San Jose CA,
Baolin Yang - Fremont CA,
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
703 14
Abstract:
A system for supporting multi-rate simulation of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) partitioning the circuit into a plurality of group circuits, each group circuit includes one or more leaf circuits, where each leaf circuit produces a predictable set of output signals with a given set of input signals, 2) storing the group circuits in a scheduled event queue in accordance with priority in time which the group circuits need to be simulated, 3) retrieving from the scheduled event queue a set of group circuits for simulation within a predetermined time period, 4) distributing the set of group circuits into a set of predefined event lists, where each of the predefined event list stores one or more group circuits of a corresponding event type, and 5) simulating the one or more group circuits in each of the predefined event list in accordance with a rate of change of signal conditions of each individual group circuit. Hence, the system provides an efficient way to support multi-rate simulation by dynamically scheduling and synchronizing multiple group simulation event types and by communicating corresponding isomorphic activities through an efficient port connectivity interface.

System And Method For Adaptive Partitioning Of Circuit Components During Simulation

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US Patent:
7024652, Apr 4, 2006
Filed:
Nov 13, 2003
Appl. No.:
10/713751
Inventors:
Bruce W. McGaughy - Fremont CA,
Peter Frey - Campbell CA,
Jun Kong - San Jose CA,
Baolin Yang - Fremont CA,
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12, 716 1, 716 11, 716 18, 703 14
Abstract:
A system for adaptive partitioning of circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first branch and the second branch for simulation, where each leaf circuit is represented by a matrix comprising a set of equations, 2) determining a strength of coupling between two or more leaf circuits of the group in accordance with a set of predetermined electrical coupling criteria, 3) if two or more leaf circuits are deemed be strongly coupled, combining the corresponding matrix of each strongly coupled leaf circuit into a combined matrix, and 4) performing computation for the two or more strongly coupled leaf circuits in accordance with the combined matrix. The system adaptively adjusts the group circuit matrix for computing a group of circuits according to the strength of coupling between the circuits. Hence, it achieves higher simulation performance by reducing either the size of the solver matrix when the circuits are loosely connected to each other, or by reducing the number of computational repetitions due to the communication of changes of signal conditions between circuits by combining the individual circuit matrices when such circuits are closely coupled to each other.
Baolin Yang from Shoreview, MN, age ~57 Get Report