Inventors:
Sushobhit Singh - Uttar Pradesh, IN
Amit Kumar - Uttar Pradesh, IN
Oleg Levitsky - San Jose CA, US
Akash Khandelwal - Cupertino CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
Abstract:
A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock ports, creating launch and capture clocks, making exclusive clock groups of the launch clock and the capture clock for opposing clock ports to avoid the launch and capture clocks for each port affecting other internal data paths within the partition block, and associating common path pessimism removal information with a source latency of the capture clock to adjust timing at an end point of the internal data path.
