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Abhishek Dube

from Fremont, CA
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Also known as:
Abe Dube, Abhishek Abhishek Dube
Phone and address:
34810 Wabash River Pl, Fremont, CA 94555
Related to:
Nikhil Dube, 40
Connected to:
Aaron R Dube, 48Alyson K Dube, 38Ana M Dube, 67Anil Dube, 56Anish R Dube, 41Anshul Dube, 40Ashli H Dube, 36Bill Dube, 44Brad A Dube, 48Bruce Dube, 73

Abhishek Dube Phones & Addresses

  • 34810 Wabash River Pl, Fremont, CA 94555
  • Redwood City, CA
  • Belmont, CA
  • Fishkill, NY
  • 316 Thurston Ave, Ithaca, NY 14850 (607) 266-8872
  • 3680 Beacon Ave APT 401, Fremont, CA 94538 (607) 272-8680

Work

Position: Sales Occupations

Education

Degree: Bachelor's degree or higher

Publications

Us Patents

Method Of Forming Source And Drain Of A Field-Effect-Transistor And Structure Thereof

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US Patent:
8084788, Dec 27, 2011
Filed:
Oct 10, 2008
Appl. No.:
12/248970
Inventors:
Judson Robert Holt - Wappingers Falls NY, US
Abhishek Dube - Fishkill NY, US
Eric C. T. Harley - Lagrangeville NY, US
Shwu-Jen Jeng - Wappingers Falls NY, US
Jeremy J Kempisty - Poughkeepsie NY, US
Hasan Munir Nayfeh - Poughkeepsie NY, US
Keith Howard Tabakman - Newburgh NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/76
H01L 29/00
US Classification:
257213, 257192, 257369, 257E27098, 257E21661
Abstract:
A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.

Process For Epitaxially Growing Epitaxial Material Regions

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US Patent:
8173524, May 8, 2012
Filed:
Jan 11, 2011
Appl. No.:
13/004201
Inventors:
Ashima B. Chakravarti - Hopewell Junction NY, US
Anthony I. Chou - Beacon NY, US
Abhishek Dube - Fishkill NY, US
Dominic J. Schepis - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/20
H01L 21/36
US Classification:
438481, 257E21461, 257E21562, 438230, 438503, 438507
Abstract:
Methods form epitaxial materials by forming at least two gate stacks on a silicon substrate and forming sidewall spacers on sides of the gate stacks. Such methods pattern a recess in the silicon substrate between adjacent ones of the gate stacks. The methods also provide a liner in a bottom of the recess, and epitaxially grow epitaxial material from sidewalls of the recess to fill the recess with the epitaxial material.

Monolayer Dopant Embedded Stressor For Advanced Cmos

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US Patent:
8236660, Aug 7, 2012
Filed:
Apr 21, 2010
Appl. No.:
12/764329
Inventors:
Kevin K. Chan - Staten Island NY, US
Abhishek Dube - Fishkill NY, US
Judson R. Holt - Wappingers Falls NY, US
Jinghong Li - Poughquag NY, US
Joseph S. Newbury - Irvington NY, US
Viorel Ontalus - Danbury CT, US
Zhengmao Zhu - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/336
US Classification:
438301, 438289, 257E21562, 257E21619, 257E21634
Abstract:
Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements.

Structure And Method For Forming Isolation And Buried Plate For Trench Capacitor

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US Patent:
8298908, Oct 30, 2012
Filed:
Feb 11, 2010
Appl. No.:
12/704084
Inventors:
Abhishek Dube - Hopewell Junction NY, US
Subramanian S. Iyer - Hopewell Junction NY, US
Babar Ali Khan - Hopewell Junction NY, US
Oh-jung Kwon - Hopewell Junction NY, US
Junedong Lee - Hopewell Junction NY, US
Paul C. Parries - Hopewell Junction NY, US
Chengwen Pei - Hopewell Junction NY, US
Gerd Pfeiffer - Hopewell Junction NY, US
Ravi M. Todi - Hopewell Junction NY, US
Geng Wang - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/20
US Classification:
438391, 257E21008
Abstract:
A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

Delta Monolayer Dopants Epitaxy For Embedded Source/Drain Silicide

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US Patent:
8299535, Oct 30, 2012
Filed:
Jun 25, 2010
Appl. No.:
12/823163
Inventors:
Kevin K. Chan - Staten Island NY, US
Abhishek Dube - Fishkill NY, US
Judson R. Holt - Wappingers Falls NY, US
Jeffrey B. Johnson - Essex Junction VT, US
Jinghong Li - Poughquag NY, US
Zhengmao Zhu - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/78
H01L 21/336
H01L 21/762
H01L 21/8234
H01L 21/8238
US Classification:
257368, 257369, 257382, 257384, 257408, 257615, 257E29255, 257E29266, 257E21409, 257E21619, 257E21562, 257E21634, 438285, 438301, 438289
Abstract:
Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

Reduced Pattern Loading For Doped Epitaxial Process And Semiconductor Structure

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US Patent:
8338279, Dec 25, 2012
Filed:
Mar 30, 2011
Appl. No.:
13/075450
Inventors:
Abhishek Dube - Fishkill NY, US
Viorel Ontalus - Danbury CT, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Zhengmao Zhu - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/20
US Classification:
438492, 438504
Abstract:
A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

Silicon Germanium Film Formation Method And Structure

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US Patent:
8354314, Jan 15, 2013
Filed:
Feb 11, 2011
Appl. No.:
13/025474
Inventors:
Ashima B. Chakravarti - Hopewell Junction NY, US
Abhishek Dube - Fishkill NY, US
Dominic J. Schepis - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8238
US Classification:
438199, 438197, 438285, 438514
Abstract:
Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

Stressed Transistor With Improved Metastability

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US Patent:
8361859, Jan 29, 2013
Filed:
Nov 9, 2010
Appl. No.:
12/942289
Inventors:
Thomas N. Adam - Slingerlands NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Abhishek Dube - Fishkill NY, US
Eric C. T. Harley - Lagrangeville NY, US
Judson R. Holt - Wappingers Falls NY, US
Alexander Reznicek - Mount Kisco NY, US
Devendra K. Sadana - Pleasantville NY, US
Dominic J. Schepis - Wappingers Falls NY, US
Matthew W. Stoker - Poughkeepsie NY, US
Keith H. Tabakman - Fishkill NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8238
US Classification:
438233, 438300, 438607
Abstract:
An embedded, strained epitaxial semiconductor material, i. e. , an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
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Abhishek Dube from Fremont, CA Get Report